[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMMul.cpp README.txt

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.49 -> 1.50
ARMMul.cpp updated: 1.2 -> 1.3
README.txt updated: 1.5 -> 1.6
---
Log message:

implement smull and umull


---
Diffs of the changes:  (+24 -5)

 ARMInstrInfo.td |   10 ++++++++++
 ARMMul.cpp      |   14 +++++++++-----
 README.txt      |    5 +++++
 3 files changed, 24 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.49 llvm/lib/Target/ARM/ARMInstrInfo.td:1.50
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.49	Sat Oct 14 08:42:53 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Mon Oct 16 11:33:29 2006
@@ -174,6 +174,16 @@
                        "mul $dst, $a, $b",
 		       [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
 
+let Defs = [R0] in {
+  def SMULL   : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+                         "smull r12, $dst, $a, $b",
+                         [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>;
+
+  def UMULL   : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
+                         "umull r12, $dst, $a, $b",
+                         [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>;
+}
+
 def bcond      : InstARM<(ops brtarget:$dst, CCOp:$cc),
 		         "b$cc $dst",
 		         [(armbr bb:$dst, imm:$cc)]>;


Index: llvm/lib/Target/ARM/ARMMul.cpp
diff -u llvm/lib/Target/ARM/ARMMul.cpp:1.2 llvm/lib/Target/ARM/ARMMul.cpp:1.3
--- llvm/lib/Target/ARM/ARMMul.cpp:1.2	Tue Sep 19 11:41:40 2006
+++ llvm/lib/Target/ARM/ARMMul.cpp	Mon Oct 16 11:33:29 2006
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Modify the ARM multiplication instructions so that Rd and Rm are distinct
+// Modify the ARM multiplication instructions so that Rd{Hi,Lo} and Rm are distinct
 //
 //===----------------------------------------------------------------------===//
 
@@ -39,7 +39,10 @@
          I != E; ++I) {
       MachineInstr *MI = I;
 
-      if (MI->getOpcode() == ARM::MUL) {
+      int Op = MI->getOpcode();
+      if (Op == ARM::MUL ||
+          Op == ARM::SMULL ||
+          Op == ARM::UMULL) {
         MachineOperand &RdOp = MI->getOperand(0);
         MachineOperand &RmOp = MI->getOperand(1);
         MachineOperand &RsOp = MI->getOperand(2);
@@ -48,7 +51,7 @@
         unsigned Rm = RmOp.getReg();
         unsigned Rs = RsOp.getReg();
 
-        if(Rd == Rm) {
+        if (Rd == Rm) {
           Changed = true;
           if (Rd != Rs) {
 	    //Rd and Rm must be distinct, but Rd can be equal to Rs.
@@ -56,9 +59,10 @@
             RmOp.setReg(Rs);
             RsOp.setReg(Rm);
           } else {
-            BuildMI(MBB, I, ARM::MOV, 3, ARM::R12).addReg(Rm).addImm(0)
+            unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
+            BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
               .addImm(ARMShift::LSL);
-            RmOp.setReg(ARM::R12);
+            RmOp.setReg(scratch);
           }
         }
       }


Index: llvm/lib/Target/ARM/README.txt
diff -u llvm/lib/Target/ARM/README.txt:1.5 llvm/lib/Target/ARM/README.txt:1.6
--- llvm/lib/Target/ARM/README.txt:1.5	Mon Oct  9 09:18:33 2006
+++ llvm/lib/Target/ARM/README.txt	Mon Oct 16 11:33:29 2006
@@ -46,3 +46,8 @@
 Only needs 8 bytes of stack space. We currently allocate 16.
 
 ----------------------------------------------------------
+
+32 x 32 -> 64 multiplications currently uses two instructions. We
+should try to declare smull and umull as returning two values.
+
+----------------------------------------------------------