[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.350 -> 1.351
---
Log message:

Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1',
which is undefined.  "0" isn't a power of 2.


---
Diffs of the changes:  (+2 -2)

 SelectionDAG.cpp |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.350 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.351
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.350	Fri Oct 13 16:12:22 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Oct 13 17:46:18 2006
@@ -910,7 +910,7 @@
                     dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
           if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
             // Perform the xform if the AND RHS is a single bit.
-            if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
+            if (isPowerOf2_64(AndRHS->getValue())) {
               return getNode(ISD::SRL, VT, N1,
                              getConstant(Log2_64(AndRHS->getValue()),
                                                    TLI.getShiftAmountTy()));
@@ -918,7 +918,7 @@
           } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) {
             // (X & 8) == 8  -->  (X & 8) >> 3
             // Perform the xform if C2 is a single bit.
-            if ((C2 & (C2-1)) == 0) {
+            if (isPowerOf2_64(C2)) {
               return getNode(ISD::SRL, VT, N1,
                              getConstant(Log2_64(C2),TLI.getShiftAmountTy()));
             }