[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrInfo.h

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86InstrInfo.cpp updated: 1.61 -> 1.62
X86InstrInfo.h updated: 1.54 -> 1.55
---
Log message:

remove some dead code


---
Diffs of the changes:  (+0 -43)

 X86InstrInfo.cpp |   33 ---------------------------------
 X86InstrInfo.h   |   10 ----------
 2 files changed, 43 deletions(-)


Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.61 llvm/lib/Target/X86/X86InstrInfo.cpp:1.62
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.61	Thu Sep 28 18:33:12 2006
+++ llvm/lib/Target/X86/X86InstrInfo.cpp	Fri Oct 13 15:40:42 2006
@@ -239,39 +239,6 @@
   }
 }
 
-
-void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
-                              MachineBasicBlock& TMBB) const {
-  BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
-}
-
-MachineBasicBlock::iterator
-X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
-  unsigned Opcode = MI->getOpcode();
-  assert(isBranch(Opcode) && "MachineInstr must be a branch");
-  unsigned ROpcode;
-  switch (Opcode) {
-  default: assert(0 && "Cannot reverse unconditional branches!");
-  case X86::JB:  ROpcode = X86::JAE; break;
-  case X86::JAE: ROpcode = X86::JB;  break;
-  case X86::JE:  ROpcode = X86::JNE; break;
-  case X86::JNE: ROpcode = X86::JE;  break;
-  case X86::JBE: ROpcode = X86::JA;  break;
-  case X86::JA:  ROpcode = X86::JBE; break;
-  case X86::JS:  ROpcode = X86::JNS; break;
-  case X86::JNS: ROpcode = X86::JS;  break;
-  case X86::JP:  ROpcode = X86::JNP; break;
-  case X86::JNP: ROpcode = X86::JP;  break;
-  case X86::JL:  ROpcode = X86::JGE; break;
-  case X86::JGE: ROpcode = X86::JL;  break;
-  case X86::JLE: ROpcode = X86::JG;  break;
-  case X86::JG:  ROpcode = X86::JLE; break;
-  }
-  MachineBasicBlock* MBB = MI->getParent();
-  MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
-  return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
-}
-
 const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const {
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   if (Subtarget->is64Bit())


Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.54 llvm/lib/Target/X86/X86InstrInfo.h:1.55
--- llvm/lib/Target/X86/X86InstrInfo.h:1.54	Fri Sep  8 01:48:29 2006
+++ llvm/lib/Target/X86/X86InstrInfo.h	Fri Oct 13 15:40:42 2006
@@ -223,16 +223,6 @@
   virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
 
 
-  /// Insert a goto (unconditional branch) sequence to TMBB, at the
-  /// end of MBB
-  virtual void insertGoto(MachineBasicBlock& MBB,
-                          MachineBasicBlock& TMBB) const;
-
-  /// Reverses the branch condition of the MachineInstr pointed by
-  /// MI. The instruction is replaced and the new MI is returned.
-  virtual MachineBasicBlock::iterator
-  reverseBranchCondition(MachineBasicBlock::iterator MI) const;
-
   const TargetRegisterClass *getPointerRegClass() const;
 
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the