[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.57 -> 1.58
AlphaISelLowering.cpp updated: 1.67 -> 1.68
AlphaISelLowering.h updated: 1.20 -> 1.21
---
Log message:

Reduce the amount of state in the lowering code and drop old pattern ISel functions

---
Diffs of the changes:  (+27 -28)

 AlphaISelDAGToDAG.cpp |   24 ++++++++++++++++++++----
 AlphaISelLowering.cpp |   25 +++++++------------------
 AlphaISelLowering.h   |    6 ------
 3 files changed, 27 insertions(+), 28 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.57 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.58
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.57	Wed Oct 11 00:13:56 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Wed Oct 11 11:24:51 2006
@@ -193,17 +193,33 @@
 /// GOT address into a register.
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
+  MachineFunction* MF = BB->getParent();
+  unsigned GP = 0;
+  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
+	ee = MF->livein_end(); ii != ee; ++ii)
+    if (ii->first == Alpha::R29) {
+      GP = ii->second;
+      break;
+    }
+  assert(GP && "GOT PTR not in liveins");
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), 
-                                AlphaLowering.getVRegGP(), 
-                                MVT::i64);
+                                GP, MVT::i64);
 }
 
 /// getRASaveReg - Grab the return address
 ///
 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
+  MachineFunction* MF = BB->getParent();
+  unsigned RA = 0;
+  for(MachineFunction::livein_iterator ii = MF->livein_begin(), 
+	ee = MF->livein_end(); ii != ee; ++ii)
+    if (ii->first == Alpha::R26) {
+      RA = ii->second;
+      break;
+    }
+  assert(RA && "RA PTR not in liveins");
   return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
-                                AlphaLowering.getVRegRA(), 
-                                MVT::i64);
+                                RA, MVT::i64);
 }
 
 /// InstructionSelectBasicBlock - This callback is invoked by


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.67 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.68
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.67	Tue Oct 10 23:29:42 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Wed Oct 11 11:24:51 2006
@@ -201,17 +201,15 @@
 
 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
 				       int &VarArgsBase,
-				       int &VarArgsOffset,
-				       unsigned int &GP,
-				       unsigned int &RA) {
+				       int &VarArgsOffset) {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   SSARegMap *RegMap = MF.getSSARegMap();
   std::vector<SDOperand> ArgValues;
   SDOperand Root = Op.getOperand(0);
 
-  GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
-  RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
+  AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass); //GP
+  AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass); //RA
 
   unsigned args_int[] = {
     Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
@@ -291,7 +289,7 @@
   return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
 }
 
-static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
+static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26, 
 				    DAG.getNode(AlphaISD::GlobalRetAddr, 
                                     MVT::i64),
@@ -386,15 +384,6 @@
   return std::make_pair(RetVal, Chain);
 }
 
-void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
-{
-  BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
-}
-void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
-{
-  BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
-}
-
 static int getUID()
 {
   static int id = 0;
@@ -408,9 +397,9 @@
   default: assert(0 && "Wasn't expecting to be able to lower this!");
   case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, 
 							   VarArgsBase,
-							   VarArgsOffset,
-							   GP, RA);
-  case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
+							   VarArgsOffset);
+
+  case ISD::RET: return LowerRET(Op,DAG);
   case ISD::JumpTable: return LowerJumpTable(Op, DAG);
 
   case ISD::SINT_TO_FP: {


Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.20 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.21
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.20	Tue Oct 10 23:29:42 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h	Wed Oct 11 11:24:51 2006
@@ -54,8 +54,6 @@
   class AlphaTargetLowering : public TargetLowering {
     int VarArgsOffset;  // What is the offset to the first vaarg
     int VarArgsBase;    // What is the base FrameIndex
-    unsigned GP; //GOT vreg
-    unsigned RA; //Return Address
     bool useITOF;
   public:
     AlphaTargetLowering(TargetMachine &TM);
@@ -81,10 +79,6 @@
       getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                         MVT::ValueType VT) const;
 
-    void restoreGP(MachineBasicBlock* BB);
-    void restoreRA(MachineBasicBlock* BB);
-    unsigned getVRegGP() { return GP; }
-    unsigned getVRegRA() { return RA; }
     bool hasITOF() { return useITOF; }
   };
 }