[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h AlphaTargetMachine.cpp AlphaTargetMachine.h
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Tue Oct 10 21:30:04 PDT 2006
Changes in directory llvm/lib/Target/Alpha:
AlphaISelDAGToDAG.cpp updated: 1.55 -> 1.56
AlphaISelLowering.cpp updated: 1.66 -> 1.67
AlphaISelLowering.h updated: 1.19 -> 1.20
AlphaTargetMachine.cpp updated: 1.33 -> 1.34
AlphaTargetMachine.h updated: 1.17 -> 1.18
---
Log message:
Jimptables working again on alpha.
As a bonus, use the GOT node instead of the AlphaISD::GOT for internal stuff.
---
Diffs of the changes: (+18 -16)
AlphaISelDAGToDAG.cpp | 5 +++--
AlphaISelLowering.cpp | 18 ++++++++----------
AlphaISelLowering.h | 3 ---
AlphaTargetMachine.cpp | 3 ++-
AlphaTargetMachine.h | 5 +++++
5 files changed, 18 insertions(+), 16 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.55 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.56
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.55 Sun Aug 27 03:12:27 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp Tue Oct 10 23:29:42 2006
@@ -99,7 +99,8 @@
public:
AlphaDAGToDAGISel(TargetMachine &TM)
- : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
+ : SelectionDAGISel(AlphaLowering),
+ AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
{}
/// getI64Imm - Return a target constant with the specified value, of type
@@ -201,7 +202,7 @@
CurDAG->getTargetFrameIndex(FI, MVT::i32),
getI64Imm(0));
}
- case AlphaISD::GlobalBaseReg: {
+ case ISD::GLOBAL_OFFSET_TABLE: {
SDOperand Result = getGlobalBaseReg();
ReplaceUses(Op, Result);
return NULL;
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.66 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.67
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.66 Mon Oct 9 15:57:24 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Tue Oct 10 23:29:42 2006
@@ -132,7 +132,6 @@
setOperationAction(ISD::JumpTable, MVT::i64, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
- setOperationAction(ISD::JumpTableRelocBase, MVT::i64, Custom);
setStackPointerRegisterToSaveRestore(Alpha::R30);
@@ -160,7 +159,6 @@
case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
case AlphaISD::RelLit: return "Alpha::RelLit";
- case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
case AlphaISD::CALL: return "Alpha::CALL";
case AlphaISD::DivCall: return "Alpha::DivCall";
@@ -177,7 +175,7 @@
const TargetMachine &TM = DAG.getTarget();
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, JTI,
- DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, JTI, Hi);
return Lo;
}
@@ -414,8 +412,6 @@
GP, RA);
case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
- case ISD::JumpTableRelocBase:
- return DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64);
case ISD::SINT_TO_FP: {
assert(MVT::i64 == Op.getOperand(0).getValueType() &&
@@ -462,7 +458,7 @@
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
- DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
return Lo;
}
@@ -474,16 +470,18 @@
// if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
if (GV->hasInternalLinkage()) {
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
- DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
return Lo;
} else
- return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
+ return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA,
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
}
case ISD::ExternalSymbol: {
return DAG.getNode(AlphaISD::RelLit, MVT::i64,
- DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
- DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
+ DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)
+ ->getSymbol(), MVT::i64),
+ DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, MVT::i64));
}
case ISD::UREM:
Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.19 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.20
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.19 Wed Jun 21 08:37:27 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h Tue Oct 10 23:29:42 2006
@@ -36,9 +36,6 @@
/// RetLit - Literal Relocation of a Global
RelLit,
- /// GlobalBaseReg - used to restore the GOT ptr
- GlobalBaseReg,
-
/// GlobalRetAddr - used to restore the return address
GlobalRetAddr,
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.33 llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.34
--- llvm/lib/Target/Alpha/AlphaTargetMachine.cpp:1.33 Sun Sep 24 14:46:56 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.cpp Tue Oct 10 23:29:42 2006
@@ -58,7 +58,8 @@
: DataLayout("e"),
FrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0),
JITInfo(*this),
- Subtarget(M, FS) {
+ Subtarget(M, FS),
+ TLInfo(*this) {
setRelocationModel(Reloc::PIC_);
}
Index: llvm/lib/Target/Alpha/AlphaTargetMachine.h
diff -u llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.17 llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.18
--- llvm/lib/Target/Alpha/AlphaTargetMachine.h:1.17 Thu Sep 7 18:39:26 2006
+++ llvm/lib/Target/Alpha/AlphaTargetMachine.h Tue Oct 10 23:29:42 2006
@@ -19,6 +19,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "AlphaInstrInfo.h"
#include "AlphaJITInfo.h"
+#include "AlphaISelLowering.h"
#include "AlphaSubtarget.h"
namespace llvm {
@@ -31,6 +32,7 @@
TargetFrameInfo FrameInfo;
AlphaJITInfo JITInfo;
AlphaSubtarget Subtarget;
+ AlphaTargetLowering TLInfo;
protected:
virtual const TargetAsmInfo *createTargetAsmInfo() const;
@@ -44,6 +46,9 @@
virtual const MRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo();
}
+ virtual TargetLowering* getTargetLowering() const {
+ return const_cast<AlphaTargetLowering*>(&TLInfo);
+ }
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual TargetJITInfo* getJITInfo() {
return &JITInfo;
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