[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.63 -> 1.64
ARMInstrInfo.td updated: 1.40 -> 1.41
---
Log message:

add double <-> int conversion


---
Diffs of the changes:  (+26 -0)

 ARMISelDAGToDAG.cpp |   18 ++++++++++++++++++
 ARMInstrInfo.td     |    8 ++++++++
 2 files changed, 26 insertions(+)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.63 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.64
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.63	Tue Oct 10 11:33:47 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Tue Oct 10 13:55:14 2006
@@ -49,6 +49,7 @@
 
   setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
 
+  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
   setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
 
   setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
@@ -96,8 +97,10 @@
       BR,
 
       FSITOS,
+      FTOSIS,
 
       FSITOD,
+      FTOSID,
 
       FUITOS,
 
@@ -148,7 +151,9 @@
   case ARMISD::CMP:           return "ARMISD::CMP";
   case ARMISD::BR:            return "ARMISD::BR";
   case ARMISD::FSITOS:        return "ARMISD::FSITOS";
+  case ARMISD::FTOSIS:        return "ARMISD::FTOSIS";
   case ARMISD::FSITOD:        return "ARMISD::FSITOD";
+  case ARMISD::FTOSID:        return "ARMISD::FTOSID";
   case ARMISD::FUITOS:        return "ARMISD::FUITOS";
   case ARMISD::FUITOD:        return "ARMISD::FUITOD";
   case ARMISD::FMRRD:         return "ARMISD::FMRRD";
@@ -586,6 +591,17 @@
   return DAG.getNode(op, vt, Tmp);
 }
 
+static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+  assert(Op.getValueType() == MVT::i32);
+  SDOperand FloatVal = Op.getOperand(0);
+  MVT::ValueType  vt = FloatVal.getValueType();
+  assert(vt == MVT::f32 || vt == MVT::f64);
+
+  ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FTOSIS : ARMISD::FTOSID;
+  SDOperand Tmp = DAG.getNode(op, MVT::f32, FloatVal);
+  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Tmp);
+}
+
 static SDOperand LowerUINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
   SDOperand IntVal  = Op.getOperand(0);
   assert(IntVal.getValueType() == MVT::i32);
@@ -607,6 +623,8 @@
     return LowerConstantPool(Op, DAG);
   case ISD::GlobalAddress:
     return LowerGlobalAddress(Op, DAG);
+  case ISD::FP_TO_SINT:
+    return LowerFP_TO_SINT(Op, DAG);
   case ISD::SINT_TO_FP:
     return LowerSINT_TO_FP(Op, DAG);
   case ISD::UINT_TO_FP:


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.40 llvm/lib/Target/ARM/ARMInstrInfo.td:1.41
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.40	Tue Oct 10 11:33:47 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Oct 10 13:55:14 2006
@@ -77,7 +77,9 @@
 def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
 
 def armfsitos      : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
+def armftosis      : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
 def armfsitod      : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
+def armftosid      : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
 def armfuitos      : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
 def armfuitod      : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
 
@@ -201,9 +203,15 @@
 def FSITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
                        "fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
 
+def FTOSIS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
+                       "ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
+
 def FSITOD  : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
                        "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
 
+def FTOSID  : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
+                       "ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
+
 def FUITOS  : InstARM<(ops FPRegs:$dst, FPRegs:$src),
                        "fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;