[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.108 -> 1.109
---
Log message:

Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.


---
Diffs of the changes:  (+4 -4)

 SparcISelDAGToDAG.cpp |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.109
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.108	Tue Sep 12 16:03:10 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp	Tue Oct  3 19:55:51 2006
@@ -137,6 +137,9 @@
   addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
   addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
 
+  // Turn FP extload into load/fextend
+  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+  
   // Custom legalize GlobalAddress nodes into LO/HI parts.
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
   setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
@@ -161,9 +164,6 @@
   setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
   setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
   
-  // Turn FP extload into load/fextend
-  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
-  
   // Sparc has no select or setcc: expand to SELECT_CC.
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
@@ -332,7 +332,7 @@
         if (ObjectVT == MVT::i32) {
           Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
         } else {
-          unsigned LoadOp =
+          ISD::LoadExtType LoadOp =
             I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
 
           // Sparc is big endian, so add an offset based on the ObjectVT.