[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/IA64:

IA64ISelDAGToDAG.cpp updated: 1.54 -> 1.55
IA64ISelLowering.cpp updated: 1.43 -> 1.44
---
Log message:

Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.


---
Diffs of the changes:  (+10 -11)

 IA64ISelDAGToDAG.cpp |    3 +--
 IA64ISelLowering.cpp |   18 +++++++++---------
 2 files changed, 10 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.55
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.54	Tue Sep 12 16:02:20 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp	Tue Oct  3 19:55:13 2006
@@ -454,8 +454,7 @@
 */
 
   case ISD::LOAD:
-  case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
-  case ISD::ZEXTLOAD: {
+  case ISD::LOADX: { // FIXME: load -1, not 1, for bools?
     SDOperand Chain = N->getOperand(0);
     SDOperand Address = N->getOperand(1);
     AddToISelQueue(Chain);


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.44
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.43	Tue Sep 12 16:02:20 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Tue Oct  3 19:55:13 2006
@@ -35,6 +35,15 @@
       // register class for predicate registers
       addRegisterClass(MVT::i1, IA64::PRRegisterClass);
 
+      setLoadXAction(ISD::EXTLOAD          , MVT::i1   , Promote);
+
+      setLoadXAction(ISD::ZEXTLOAD         , MVT::i1   , Expand);
+
+      setLoadXAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
+      setLoadXAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
+      setLoadXAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
+      setLoadXAction(ISD::SEXTLOAD         , MVT::i32  , Expand);
+
       setOperationAction(ISD::BRIND            , MVT::i64,   Expand);
       setOperationAction(ISD::BR_CC            , MVT::Other, Expand);
       setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);
@@ -50,15 +59,6 @@
       setSetCCResultType(MVT::i1);
       setShiftAmountType(MVT::i64);
 
-      setOperationAction(ISD::EXTLOAD          , MVT::i1   , Promote);
-
-      setOperationAction(ISD::ZEXTLOAD         , MVT::i1   , Expand);
-
-      setOperationAction(ISD::SEXTLOAD         , MVT::i1   , Expand);
-      setOperationAction(ISD::SEXTLOAD         , MVT::i8   , Expand);
-      setOperationAction(ISD::SEXTLOAD         , MVT::i16  , Expand);
-      setOperationAction(ISD::SEXTLOAD         , MVT::i32  , Expand);
-
       setOperationAction(ISD::FREM             , MVT::f32  , Expand);
       setOperationAction(ISD::FREM             , MVT::f64  , Expand);