[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMRegisterInfo.td
Rafael Espindola
rafael.espindola at gmail.com
Mon Oct 2 12:31:13 PDT 2006
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.48 -> 1.49
ARMInstrInfo.td updated: 1.29 -> 1.30
ARMRegisterInfo.td updated: 1.4 -> 1.5
---
Log message:
fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers
---
Diffs of the changes: (+58 -25)
ARMISelDAGToDAG.cpp | 41 ++++++++++++++++++++++++++++++++---------
ARMInstrInfo.td | 10 ++++++++++
ARMRegisterInfo.td | 32 ++++++++++++++++----------------
3 files changed, 58 insertions(+), 25 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.48 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.49
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.48 Fri Sep 29 16:20:15 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Mon Oct 2 14:30:56 2006
@@ -82,7 +82,11 @@
BR,
- FSITOS
+ FSITOS,
+
+ FSITOD,
+
+ FMRRD
};
}
}
@@ -115,6 +119,8 @@
case ARMISD::CMP: return "ARMISD::CMP";
case ARMISD::BR: return "ARMISD::BR";
case ARMISD::FSITOS: return "ARMISD::FSITOS";
+ case ARMISD::FSITOD: return "ARMISD::FSITOD";
+ case ARMISD::FMRRD: return "ARMISD::FMRRD";
}
}
@@ -237,6 +243,9 @@
static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
SDOperand Copy;
SDOperand Chain = Op.getOperand(0);
+ SDOperand R0 = DAG.getRegister(ARM::R0, MVT::i32);
+ SDOperand R1 = DAG.getRegister(ARM::R1, MVT::i32);
+
switch(Op.getNumOperands()) {
default:
assert(0 && "Do not know how to return this many arguments!");
@@ -248,13 +257,24 @@
case 3: {
SDOperand Val = Op.getOperand(1);
assert(Val.getValueType() == MVT::i32 ||
- Val.getValueType() == MVT::f32);
+ Val.getValueType() == MVT::f32 ||
+ Val.getValueType() == MVT::f64);
+
+ if (Val.getValueType() == MVT::f64) {
+ SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
+ SDOperand Ops[] = {Chain, R0, R1, Val};
+ Copy = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+ } else {
+ if (Val.getValueType() == MVT::f32)
+ Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
+ Copy = DAG.getCopyToReg(Chain, R0, Val, SDOperand());
+ }
- if (Val.getValueType() == MVT::f32)
- Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
- Copy = DAG.getCopyToReg(Chain, ARM::R0, Val, SDOperand());
- if (DAG.getMachineFunction().liveout_empty())
+ if (DAG.getMachineFunction().liveout_empty()) {
DAG.getMachineFunction().addLiveOut(ARM::R0);
+ if (Val.getValueType() == MVT::f64)
+ DAG.getMachineFunction().addLiveOut(ARM::R1);
+ }
break;
}
case 5:
@@ -421,12 +441,15 @@
}
static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
- SDOperand IntVal = Op.getOperand(0);
+ SDOperand IntVal = Op.getOperand(0);
assert(IntVal.getValueType() == MVT::i32);
- assert(Op.getValueType() == MVT::f32);
+ MVT::ValueType vt = Op.getValueType();
+ assert(vt == MVT::f32 ||
+ vt == MVT::f64);
SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, IntVal);
- return DAG.getNode(ARMISD::FSITOS, MVT::f32, Tmp);
+ ARMISD::NodeType op = vt == MVT::f32 ? ARMISD::FSITOS : ARMISD::FSITOD;
+ return DAG.getNode(op, vt, Tmp);
}
SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.29 llvm/lib/Target/ARM/ARMInstrInfo.td:1.30
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.29 Fri Sep 29 16:20:15 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Mon Oct 2 14:30:56 2006
@@ -75,6 +75,10 @@
def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
+def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
+
+def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
+def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd, [SDNPHasChain, SDNPOutFlag]>;
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
@@ -164,5 +168,11 @@
def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
"fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
+def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
+ "fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
+
def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
"fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
+
+def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
+ "fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.4 llvm/lib/Target/ARM/ARMRegisterInfo.td:1.5
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.4 Fri Sep 29 16:20:16 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td Mon Oct 2 14:30:56 2006
@@ -88,22 +88,22 @@
def S31 : Rf<31, "S31">, DwarfRegNum<95>;
// Aliases of the S* registers used to hold 64-bit fp values (doubles)
-def D0 : Rd< 0, "S0", [S0, S1]>, DwarfRegNum<64>;
-def D1 : Rd< 2, "S2", [S2, S3]>, DwarfRegNum<66>;
-def D2 : Rd< 4, "S4", [S4, S5]>, DwarfRegNum<68>;
-def D3 : Rd< 6, "S6", [S6, S7]>, DwarfRegNum<70>;
-def D4 : Rd< 8, "S8", [S8, S9]>, DwarfRegNum<72>;
-def D5 : Rd<10, "S10", [S10, S11]>, DwarfRegNum<74>;
-def D6 : Rd<12, "S12", [S12, S13]>, DwarfRegNum<76>;
-def D7 : Rd<14, "S14", [S14, S15]>, DwarfRegNum<78>;
-def D8 : Rd<16, "S16", [S16, S17]>, DwarfRegNum<80>;
-def D9 : Rd<18, "S18", [S18, S19]>, DwarfRegNum<82>;
-def D10 : Rd<20, "S20", [S20, S21]>, DwarfRegNum<84>;
-def D11 : Rd<22, "S22", [S22, S23]>, DwarfRegNum<86>;
-def D12 : Rd<24, "S24", [S24, S25]>, DwarfRegNum<88>;
-def D13 : Rd<26, "S26", [S26, S27]>, DwarfRegNum<90>;
-def D14 : Rd<28, "S28", [S28, S29]>, DwarfRegNum<92>;
-def D15 : Rd<30, "S30", [S30, S31]>, DwarfRegNum<94>;
+def D0 : Rd< 0, "D0", [S0, S1]>, DwarfRegNum<64>;
+def D1 : Rd< 2, "D1", [S2, S3]>, DwarfRegNum<66>;
+def D2 : Rd< 4, "D2", [S4, S5]>, DwarfRegNum<68>;
+def D3 : Rd< 6, "D3", [S6, S7]>, DwarfRegNum<70>;
+def D4 : Rd< 8, "D4", [S8, S9]>, DwarfRegNum<72>;
+def D5 : Rd<10, "D5", [S10, S11]>, DwarfRegNum<74>;
+def D6 : Rd<12, "D6", [S12, S13]>, DwarfRegNum<76>;
+def D7 : Rd<14, "D7", [S14, S15]>, DwarfRegNum<78>;
+def D8 : Rd<16, "D8", [S16, S17]>, DwarfRegNum<80>;
+def D9 : Rd<18, "D9", [S18, S19]>, DwarfRegNum<82>;
+def D10 : Rd<20, "D10", [S20, S21]>, DwarfRegNum<84>;
+def D11 : Rd<22, "D11", [S22, S23]>, DwarfRegNum<86>;
+def D12 : Rd<24, "D12", [S24, S25]>, DwarfRegNum<88>;
+def D13 : Rd<26, "D13", [S26, S27]>, DwarfRegNum<90>;
+def D14 : Rd<28, "D14", [S28, S29]>, DwarfRegNum<92>;
+def D15 : Rd<30, "D15", [S30, S31]>, DwarfRegNum<94>;
// Register classes.
//
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