[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaLLRP.cpp
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Wed Sep 20 13:09:08 PDT 2006
Changes in directory llvm/lib/Target/Alpha:
AlphaLLRP.cpp updated: 1.1 -> 1.2
---
Log message:
Account for pseudo-ops correctly
---
Diffs of the changes: (+51 -44)
AlphaLLRP.cpp | 95 +++++++++++++++++++++++++++++++---------------------------
1 files changed, 51 insertions(+), 44 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaLLRP.cpp
diff -u llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.1 llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.2
--- llvm/lib/Target/Alpha/AlphaLLRP.cpp:1.1 Mon Sep 18 14:44:29 2006
+++ llvm/lib/Target/Alpha/AlphaLLRP.cpp Wed Sep 20 15:08:52 2006
@@ -58,7 +58,6 @@
case Alpha::LDQ: case Alpha::LDL:
case Alpha::LDWU: case Alpha::LDBU:
case Alpha::LDT: case Alpha::LDS:
-
case Alpha::STQ: case Alpha::STL:
case Alpha::STW: case Alpha::STB:
case Alpha::STT: case Alpha::STS:
@@ -89,49 +88,57 @@
Changed = true; nopintro += 2;
count += 2;
} else if (prev[2]
- && prev[2]->getOperand(2).getReg() ==
- MI->getOperand(2).getReg()
- && prev[2]->getOperand(1).getImmedValue() ==
- MI->getOperand(1).getImmedValue()) {
- prev[0] = prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
- .addReg(Alpha::R31);
- Changed = true; nopintro += 3;
- count += 3;
- }
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = MI;
- break;
- }
- //fall through
- case Alpha::BR:
- case Alpha::JMP:
- ub = true;
- //fall through
- default:
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = 0;
- break;
- }
- }
- if (ub || AlignAll) {
- //we can align stuff for free at this point
- while (count % 4) {
- BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
- .addReg(Alpha::R31).addReg(Alpha::R31);
- ++count;
- ++nopalign;
- prev[0] = prev[1];
- prev[1] = prev[2];
- prev[2] = 0;
- }
- }
+ && prev[2]->getOperand(2).getReg() ==
+ MI->getOperand(2).getReg()
+ && prev[2]->getOperand(1).getImmedValue() ==
+ MI->getOperand(1).getImmedValue()) {
+ prev[0] = prev[1] = prev[2] = 0;
+ BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ .addReg(Alpha::R31);
+ Changed = true; nopintro += 3;
+ count += 3;
+ }
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = MI;
+ break;
+ }
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
+ break;
+ case Alpha::ALTENT:
+ case Alpha::MEMLABEL:
+ case Alpha::PCLABEL:
+ --count;
+ break;
+ case Alpha::BR:
+ case Alpha::JMP:
+ ub = true;
+ //fall through
+ default:
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
+ break;
+ }
+ }
+ if (ub || AlignAll) {
+ //we can align stuff for free at this point
+ while (count % 4) {
+ BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
+ .addReg(Alpha::R31).addReg(Alpha::R31);
+ ++count;
+ ++nopalign;
+ prev[0] = prev[1];
+ prev[1] = prev[2];
+ prev[2] = 0;
+ }
+ }
}
return Changed;
}
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