[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt
Chris Lattner
sabre at nondot.org
Tue Sep 19 20:59:40 PDT 2006
Changes in directory llvm/lib/Target/PowerPC:
README.txt updated: 1.95 -> 1.96
---
Log message:
Add a note that we should match rlwnm better
---
Diffs of the changes: (+34 -0)
README.txt | 34 ++++++++++++++++++++++++++++++++++
1 files changed, 34 insertions(+)
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.95 llvm/lib/Target/PowerPC/README.txt:1.96
--- llvm/lib/Target/PowerPC/README.txt:1.95 Thu Sep 14 15:56:30 2006
+++ llvm/lib/Target/PowerPC/README.txt Tue Sep 19 22:59:25 2006
@@ -6,6 +6,40 @@
===-------------------------------------------------------------------------===
+We only produce the rlwnm instruction for rotate instructions. We should
+at least match stuff like:
+
+unsigned rot_and(unsigned X, int Y) {
+ unsigned T = (X << Y) | (X >> (32-Y));
+ T &= 127;
+ return T;
+}
+
+_foo3:
+ rlwnm r2, r3, r4, 0, 31
+ rlwinm r3, r2, 0, 25, 31
+ blr
+
+... which is the basic pattern that should be written in the instr. It may
+also be useful for stuff like:
+
+long long foo2(long long X, int C) {
+ return X << (C&~32);
+}
+
+which currently produces:
+
+_foo2:
+ rlwinm r2, r5, 0, 27, 25
+ subfic r5, r2, 32
+ slw r3, r3, r2
+ srw r5, r4, r5
+ or r3, r3, r5
+ slw r4, r4, r2
+ blr
+
+===-------------------------------------------------------------------------===
+
Support 'update' load/store instructions. These are cracked on the G5, but are
still a codesize win.
More information about the llvm-commits
mailing list