[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/Sparc:

SparcISelDAGToDAG.cpp updated: 1.104 -> 1.105
---
Log message:

Match tblgen changes.

---
Diffs of the changes:  (+8 -6)

 SparcISelDAGToDAG.cpp |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
diff -u llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.104 llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.105
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp:1.104	Wed Aug 16 02:29:40 2006
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp	Fri Aug 25 20:07:58 2006
@@ -1076,9 +1076,10 @@
   case ISD::SDIV:
   case ISD::UDIV: {
     // FIXME: should use a custom expander to expose the SRA to the dag.
-    SDOperand DivLHS, DivRHS;
-    AddToQueue(DivLHS, N->getOperand(0));
-    AddToQueue(DivRHS, N->getOperand(1));
+    SDOperand DivLHS = N->getOperand(0);
+    SDOperand DivRHS = N->getOperand(1);
+    AddToISelQueue(DivLHS);
+    AddToISelQueue(DivRHS);
     
     // Set the Y register to the high-part.
     SDOperand TopPart;
@@ -1099,9 +1100,10 @@
   case ISD::MULHU:
   case ISD::MULHS: {
     // FIXME: Handle mul by immediate.
-    SDOperand MulLHS, MulRHS;
-    AddToQueue(MulLHS, N->getOperand(0));
-    AddToQueue(MulRHS, N->getOperand(1));
+    SDOperand MulLHS = N->getOperand(0);
+    SDOperand MulRHS = N->getOperand(1);
+    AddToISelQueue(MulLHS);
+    AddToISelQueue(MulRHS);
     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
     SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
                                         MulLHS, MulRHS);