[llvm-commits] CVS: llvm/lib/Target/ARM/ARM.h ARMAsmPrinter.cpp ARMISelDAGToDAG.cpp ARMInstrInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARM.h updated: 1.1 -> 1.2
ARMAsmPrinter.cpp updated: 1.12 -> 1.13
ARMISelDAGToDAG.cpp updated: 1.34 -> 1.35
ARMInstrInfo.td updated: 1.19 -> 1.20
---
Log message:

create a generic bcond instruction that has a conditional code argument


---
Diffs of the changes:  (+34 -8)

 ARM.h               |   14 ++++++++++++++
 ARMAsmPrinter.cpp   |    3 ++-
 ARMISelDAGToDAG.cpp |   13 ++++++++++---
 ARMInstrInfo.td     |   12 ++++++++----
 4 files changed, 34 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/ARM/ARM.h
diff -u llvm/lib/Target/ARM/ARM.h:1.1 llvm/lib/Target/ARM/ARM.h:1.2
--- llvm/lib/Target/ARM/ARM.h:1.1	Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARM.h	Thu Aug 24 11:13:15 2006
@@ -20,6 +20,20 @@
 #include <cassert>
 
 namespace llvm {
+  // Enums corresponding to ARM condition codes
+  namespace ARMCC {
+    enum CondCodes {
+      NE
+    };
+  }
+
+  static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
+    switch (CC) {
+    default: assert(0 && "Unknown condition code");
+    case ARMCC::NE:  return "ne";
+    }
+  }
+
   class FunctionPass;
   class TargetMachine;
 


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.12 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.13
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.12	Thu Aug 24 08:45:54 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Thu Aug 24 11:13:15 2006
@@ -201,7 +201,8 @@
 }
 
 void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
-  assert(0 && "not implemented");
+  int CC = (int)MI->getOperand(opNum).getImmedValue();
+  O << ARMCondCodeToString((ARMCC::CondCodes)CC);
 }
 
 bool ARMAsmPrinter::doInitialization(Module &M) {


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.34 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.35
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.34	Thu Aug 24 08:45:54 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Thu Aug 24 11:13:15 2006
@@ -79,6 +79,14 @@
   }
 }
 
+/// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
+static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
+  switch (CC) {
+  default: assert(0 && "Unknown condition code!");
+  case ISD::SETNE:  return ARMCC::NE;
+  }
+}
+
 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   default: return 0;
@@ -322,11 +330,10 @@
   SDOperand    LHS = Op.getOperand(2);
   SDOperand    RHS = Op.getOperand(3);
   SDOperand   Dest = Op.getOperand(4);
-
-  assert(CC == ISD::SETNE);
+  SDOperand  ARMCC = DAG.getConstant(DAGCCToARMCC(CC), MVT::i32);
 
   SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
-  return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, Cmp);
+  return DAG.getNode(ARMISD::BR, MVT::Other, Chain, Dest, ARMCC, Cmp);
 }
 
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.19 llvm/lib/Target/ARM/ARMInstrInfo.td:1.20
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.19	Thu Aug 24 08:45:55 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Thu Aug 24 11:13:15 2006
@@ -39,6 +39,10 @@
 
 def brtarget : Operand<OtherVT>;
 
+// Operand for printing out a condition code.
+let PrintMethod = "printCCOperand" in
+  def CCOp : Operand<i32>;
+
 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
 def callseq_start  : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
     		             [SDNPHasChain, SDNPOutFlag]>;
@@ -52,7 +56,7 @@
 	                   [SDNPHasChain, SDNPOptInFlag]>;
 def armselect      : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
 
-def SDTarmbr       : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
+def SDTarmbr       : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
 def armbr          : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
 
 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
@@ -112,9 +116,9 @@
 		         [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
 }
 
-def bne    : InstARM<(ops brtarget:$dst),
-		     "bne $dst",
-		     [(armbr bb:$dst)]>;
+def bcond      : InstARM<(ops brtarget:$dst, CCOp:$cc),
+		         "b$cc $dst",
+		         [(armbr bb:$dst, imm:$cc)]>;
 
 def cmp      : InstARM<(ops IntRegs:$a, IntRegs:$b),
 	               "cmp $a, $b",