[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMTargetMachine.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.32 -> 1.33
ARMInstrInfo.td updated: 1.17 -> 1.18
ARMTargetMachine.cpp updated: 1.5 -> 1.6
---
Log message:

initial support for select


---
Diffs of the changes:  (+42 -1)

 ARMISelDAGToDAG.cpp  |   26 +++++++++++++++++++++++++-
 ARMInstrInfo.td      |   14 ++++++++++++++
 ARMTargetMachine.cpp |    3 +++
 3 files changed, 42 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.32 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.33
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.32	Sat Aug 19 20:49:49 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Mon Aug 21 17:00:32 2006
@@ -51,6 +51,9 @@
   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
   setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
 
+  setOperationAction(ISD::SETCC, MVT::i32, Expand);
+  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
+
   setSchedulingPreference(SchedulingForRegPressure);
   computeRegisterProperties();
 }
@@ -64,7 +67,11 @@
       CALL,
 
       /// Return with a flag operand.
-      RET_FLAG
+      RET_FLAG,
+
+      CMP,
+
+      SELECT
     };
   }
 }
@@ -74,6 +81,8 @@
   default: return 0;
   case ARMISD::CALL:          return "ARMISD::CALL";
   case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
+  case ARMISD::SELECT:        return "ARMISD::SELECT";
+  case ARMISD::CMP:           return "ARMISD::CMP";
   }
 }
 
@@ -290,6 +299,19 @@
   return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
 }
 
+static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
+  SDOperand LHS = Op.getOperand(0);
+  SDOperand RHS = Op.getOperand(1);
+  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
+  SDOperand TrueVal = Op.getOperand(2);
+  SDOperand FalseVal = Op.getOperand(3);
+
+  assert(CC == ISD::SETEQ);
+
+  SDOperand Cmp = DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
+  return DAG.getNode(ARMISD::SELECT, MVT::i32, FalseVal, TrueVal, Cmp);
+}
+
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default:
@@ -305,6 +327,8 @@
     return LowerCALL(Op, DAG);
   case ISD::RET:
     return LowerRET(Op, DAG);
+  case ISD::SELECT_CC:
+    return LowerSELECT_CC(Op, DAG);
   }
 }
 


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.17 llvm/lib/Target/ARM/ARMInstrInfo.td:1.18
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.17	Mon Aug 21 08:58:59 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Mon Aug 21 17:00:32 2006
@@ -48,6 +48,10 @@
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 def retflag        : SDNode<"ARMISD::RET_FLAG", SDTRet,
 	                   [SDNPHasChain, SDNPOptInFlag]>;
+def armselect      : SDNode<"ARMISD::SELECT", SDTIntBinOp, [SDNPInFlag, SDNPOutFlag]>;
+
+def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
+def armcmp       : SDNode<"ARMISD::CMP",  SDTVoidBinOp, [SDNPOutFlag]>;
 
 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
                             "!ADJCALLSTACKUP $amt",
@@ -96,3 +100,13 @@
 def andrr     : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
 		       "and $dst, $a, $b",
 		       [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
+
+let isTwoAddress = 1 in {
+  def moveq    : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true),
+	                 "moveq $dst, $true",
+		         [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false))]>;
+}
+
+def cmp      : InstARM<(ops IntRegs:$a, IntRegs:$b),
+	               "cmp $a, $b",
+		       [(armcmp IntRegs:$a, IntRegs:$b)]>;


Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp
diff -u llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.5 llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.6
--- llvm/lib/Target/ARM/ARMTargetMachine.cpp:1.5	Wed Aug 16 09:43:33 2006
+++ llvm/lib/Target/ARM/ARMTargetMachine.cpp	Mon Aug 21 17:00:32 2006
@@ -61,6 +61,9 @@
   if (!Fast)
     PM.add(createLoopStrengthReducePass());
 
+  if (!Fast)
+    PM.add(createCFGSimplificationPass());
+
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());