[llvm-commits] CVS: llvm/lib/Target/IA64/IA64RegisterInfo.cpp IA64RegisterInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/IA64:

IA64RegisterInfo.cpp updated: 1.20 -> 1.21
IA64RegisterInfo.td updated: 1.16 -> 1.17
---
Log message:

Constify some methods.  Patch provided by Anton Vayvod, thanks!


---
Diffs of the changes:  (+9 -9)

 IA64RegisterInfo.cpp |    2 +-
 IA64RegisterInfo.td  |   16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.20 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.21
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.20	Wed May 17 19:12:11 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Thu Aug 17 17:00:08 2006
@@ -113,7 +113,7 @@
 // pointer register.  This is true if the function has variable sized allocas or
 // if frame pointer elimination is disabled.
 //
-static bool hasFP(MachineFunction &MF) {
+static bool hasFP(const MachineFunction &MF) {
   return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
 }
 


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.16 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.17
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.16	Fri Mar 24 15:15:58 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Thu Aug 17 17:00:08 2006
@@ -422,18 +422,18 @@
 	r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down)
   {
     let MethodProtos = [{
-    iterator allocation_order_begin(MachineFunction &MF) const;
-    iterator allocation_order_end(MachineFunction &MF) const;
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
     GRClass::iterator
-    GRClass::allocation_order_begin(MachineFunction &MF) const {
+    GRClass::allocation_order_begin(const MachineFunction &MF) const {
 	// hide the 8 out? registers appropriately:
 	return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
       }
 
       GRClass::iterator
-      GRClass::allocation_order_end(MachineFunction &MF) const {
+      GRClass::allocation_order_end(const MachineFunction &MF) const {
 	int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc
 
 	// we also can't allocate registers for use as locals if they're
@@ -472,17 +472,17 @@
     let Alignment=128;
 
     let MethodProtos = [{
-    iterator allocation_order_begin(MachineFunction &MF) const;
-    iterator allocation_order_end(MachineFunction &MF) const;
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
   }];
   let MethodBodies = [{
     FPClass::iterator
-    FPClass::allocation_order_begin(MachineFunction &MF) const {
+    FPClass::allocation_order_begin(const MachineFunction &MF) const {
 	return begin(); // we don't hide any FP regs from the start
       }
 
       FPClass::iterator
-      FPClass::allocation_order_end(MachineFunction &MF) const {
+      FPClass::allocation_order_end(const MachineFunction &MF) const {
 	return end()-2; // we hide regs F0, F1 from the end 
       }
   }];