[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.10 -> 1.11
ARMISelDAGToDAG.cpp updated: 1.30 -> 1.31
ARMInstrInfo.td updated: 1.15 -> 1.16
ARMRegisterInfo.cpp updated: 1.15 -> 1.16
---
Log message:

add a "load effective address"


---
Diffs of the changes:  (+30 -10)

 ARMAsmPrinter.cpp   |   24 ++++++++++++++++--------
 ARMISelDAGToDAG.cpp |    5 +++++
 ARMInstrInfo.td     |    8 +++++++-
 ARMRegisterInfo.cpp |    3 ++-
 4 files changed, 30 insertions(+), 10 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.10 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.11
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.10	Tue Aug  1 13:53:10 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Thu Aug 17 12:09:40 2006
@@ -59,19 +59,27 @@
       return "ARM Assembly Printer";
     }
 
-    void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
-      const MachineOperand &MO1 = MI->getOperand(OpNo);
-      const MachineOperand &MO2 = MI->getOperand(OpNo + 1);
+    void printMemRegImm(const MachineInstr *MI, int opNum,
+			const char *Modifier = NULL) {
+      const MachineOperand &MO1 = MI->getOperand(opNum);
+      const MachineOperand &MO2 = MI->getOperand(opNum + 1);
       assert(MO1.isImmediate());
+      bool arith = false;
+      if (Modifier != NULL) {
+	assert(strcmp(Modifier, "arith") == 0);
+	arith = true;
+      }
 
       if (MO2.isConstantPoolIndex()) {
-	printOperand(MI, OpNo + 1);
+	printOperand(MI, opNum + 1);
       } else if (MO2.isRegister()) {
-	O << '[';
-	printOperand(MI, OpNo + 1);
+	if(!arith)
+	  O << '[';
+	printOperand(MI, opNum + 1);
 	O << ", ";
-	printOperand(MI, OpNo);
-	O << ']';
+	printOperand(MI, opNum);
+	if(!arith)
+	  O << ']';
       } else {
 	assert(0 && "Invalid Operand Type");
       }


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.30 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.31
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.30	Wed Aug 16 09:43:33 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Thu Aug 17 12:09:40 2006
@@ -358,6 +358,11 @@
 //register plus/minus 12 bit offset
 bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
 				    SDOperand &Base) {
+  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
+    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+    Offset = CurDAG->getTargetConstant(0, MVT::i32);
+    return true;
+  }
   if (N.getOpcode() == ISD::ADD) {
     short imm = 0;
     if (isInt12Immediate(N.getOperand(1), imm)) {


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.15 llvm/lib/Target/ARM/ARMInstrInfo.td:1.16
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.15	Wed Aug 16 09:43:33 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Thu Aug 17 12:09:40 2006
@@ -21,7 +21,7 @@
 
 // Define ARM specific addressing mode.
 //register plus/minus 12 bit offset
-def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrRegImm", []>;
+def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
 //register plus scaled register
 //def raddr  : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
 
@@ -83,6 +83,12 @@
                        "add $dst, $a, $b",
 		       [(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
 
+// "LEA" forms of add
+def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
+			 "add $dst, ${addr:arith}",
+                	 [(set IntRegs:$dst, iaddr:$addr)]>;
+
+
 def subri   : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
                        "sub $dst, $a, $b",
 		       [(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.15 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.16
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.15	Wed Aug 16 09:43:33 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Thu Aug 17 12:09:40 2006
@@ -89,7 +89,8 @@
   MachineFunction &MF = *MBB.getParent();
 
   assert (MI.getOpcode() == ARM::ldr ||
-	  MI.getOpcode() == ARM::str);
+	  MI.getOpcode() == ARM::str ||
+	  MI.getOpcode() == ARM::lea_addri);
 
   unsigned FrameIdx = 2;
   unsigned OffIdx = 1;