[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.24 -> 1.25
ARMRegisterInfo.cpp updated: 1.12 -> 1.13
---
Log message:

fix the spill code


---
Diffs of the changes:  (+15 -7)

 ARMISelDAGToDAG.cpp |    6 ++++++
 ARMRegisterInfo.cpp |   16 +++++++++-------
 2 files changed, 15 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.24 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.25
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.24	Tue Aug  8 08:02:29 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Wed Aug  9 11:41:12 2006
@@ -148,6 +148,12 @@
   Ops.push_back(Chain);
   Ops.push_back(Callee);
 
+  // Add argument registers to the end of the list so that they are known live
+  // into the call.
+  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
+    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
+                                  RegsToPass[i].second.getValueType()));
+
   unsigned CallOpc = ARMISD::CALL;
   if (InFlag.Val)
     Ops.push_back(InFlag);


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.12 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.13
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.12	Wed Aug  9 08:15:47 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Wed Aug  9 11:41:12 2006
@@ -31,9 +31,8 @@
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                     unsigned SrcReg, int FI,
                     const TargetRegisterClass *RC) const {
-  // On the order of operands here: think "[FI + 0] = SrcReg".
   assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::str, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
+  BuildMI(MBB, I, ARM::str, 3).addReg(SrcReg).addImm(0).addFrameIndex(FI);
 }
 
 void ARMRegisterInfo::
@@ -41,7 +40,7 @@
                      unsigned DestReg, int FI,
                      const TargetRegisterClass *RC) const {
   assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::ldr, 2, DestReg).addFrameIndex(FI).addImm(0);
+  BuildMI(MBB, I, ARM::ldr, 2, DestReg).addImm(0).addFrameIndex(FI);
 }
 
 void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -81,7 +80,8 @@
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
 
-  assert (MI.getOpcode() == ARM::ldr);
+  assert (MI.getOpcode() == ARM::ldr ||
+	  MI.getOpcode() == ARM::str);
 
   unsigned FrameIdx = 2;
   unsigned OffIdx = 1;
@@ -93,6 +93,11 @@
 
   unsigned StackSize = MF.getFrameInfo()->getStackSize();
 
+  //<hack>
+  if (Offset < 0)
+    Offset -= 4;
+  //</hack>
+
   Offset += StackSize;
 
   assert (Offset >= 0);
@@ -121,9 +126,6 @@
   MachineFrameInfo  *MFI = MF.getFrameInfo();
   int           NumBytes = (int) MFI->getStackSize();
 
-  //hack
-  assert(NumBytes == 0);
-
   if (MFI->hasCalls()) {
     // We reserve argument space for call sites in the function immediately on
     // entry to the current function.  This eliminates the need for add/sub