[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Chris Lattner
lattner at cs.uiuc.edu
Mon Aug 7 19:24:05 PDT 2006
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.179 -> 1.180
LegalizeDAG.cpp updated: 1.385 -> 1.386
SelectionDAG.cpp updated: 1.320 -> 1.321
SelectionDAGISel.cpp updated: 1.267 -> 1.268
---
Log message:
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
---
Diffs of the changes: (+177 -275)
DAGCombiner.cpp | 76 +++++++++++++----------
LegalizeDAG.cpp | 87 ++++++++++++++-------------
SelectionDAG.cpp | 163 ++++++++++-----------------------------------------
SelectionDAGISel.cpp | 126 ++++++++++++++++-----------------------
4 files changed, 177 insertions(+), 275 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.179 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.180
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.179 Tue Jul 25 15:44:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Aug 7 21:23:41 2006
@@ -510,7 +510,7 @@
}
SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
bool Changed = false;
// If the token factor has two operands and one is the entry token, replace
@@ -539,7 +539,7 @@
}
}
if (Changed)
- return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
+ return DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
return SDOperand();
}
@@ -1284,7 +1284,7 @@
// Produce a vector of zeros.
SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
- return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+ return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
}
@@ -1953,14 +1953,14 @@
// If this is a conversion of N elements of one type to N elements of another
// type, convert each element. This handles FP<->INT cases.
if (SrcBitSize == DstBitSize) {
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
AddToWorkList(Ops.back().Val);
}
Ops.push_back(*(BV->op_end()-2)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT));
- return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
}
// Otherwise, we're growing or shrinking the elements. To avoid having to
@@ -1992,7 +1992,7 @@
if (SrcBitSize < DstBitSize) {
unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
i += NumInputsPerOutput) {
bool isLE = TLI.isLittleEndian();
@@ -2016,13 +2016,13 @@
Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
- return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
}
// Finally, this must be the case where we are shrinking elements: each input
// turns into multiple outputs.
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
for (unsigned j = 0; j != NumOutputsPerInput; ++j)
@@ -2043,7 +2043,7 @@
}
Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
- return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
}
@@ -2448,10 +2448,11 @@
// vector with the inserted element.
if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
- std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+ SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
if (Elt < Ops.size())
Ops[Elt] = InVal;
- return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
+ return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
+ &Ops[0], Ops.size());
}
return SDOperand();
@@ -2468,10 +2469,11 @@
// vector with the inserted element.
if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
- std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
+ SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
if (Elt < Ops.size()-2)
Ops[Elt] = InVal;
- return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
+ return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
+ &Ops[0], Ops.size());
}
return SDOperand();
@@ -2524,7 +2526,7 @@
// If everything is good, we can make a shuffle operation.
if (VecIn1.Val) {
- std::vector<SDOperand> BuildVecIndices;
+ SmallVector<SDOperand, 8> BuildVecIndices;
for (unsigned i = 0; i != NumInScalars; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
@@ -2549,10 +2551,10 @@
BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
// Return the new VVECTOR_SHUFFLE node.
- std::vector<SDOperand> Ops;
- Ops.push_back(VecIn1);
+ SDOperand Ops[5];
+ Ops[0] = VecIn1;
if (VecIn2.Val) {
- Ops.push_back(VecIn2);
+ Ops[1] = VecIn2;
} else {
// Use an undef vbuild_vector as input for the second operand.
std::vector<SDOperand> UnOps(NumInScalars,
@@ -2560,13 +2562,15 @@
cast<VTSDNode>(EltType)->getVT()));
UnOps.push_back(NumElts);
UnOps.push_back(EltType);
- Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
- AddToWorkList(Ops.back().Val);
- }
- Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
- Ops.push_back(NumElts);
- Ops.push_back(EltType);
- return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+ Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &UnOps[0], UnOps.size());
+ AddToWorkList(Ops[1].Val);
+ }
+ Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &BuildVecIndices[0], BuildVecIndices.size());
+ Ops[3] = NumElts;
+ Ops[4] = EltType;
+ return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
}
return SDOperand();
@@ -2668,7 +2672,7 @@
return DAG.getNode(ISD::UNDEF, N->getValueType(0));
// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
// first operand.
- std::vector<SDOperand> MappedOps;
+ SmallVector<SDOperand, 8> MappedOps;
for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -2680,7 +2684,7 @@
}
}
ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
- MappedOps);
+ &MappedOps[0], MappedOps.size());
AddToWorkList(ShufMask.Val);
return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
N0,
@@ -2785,7 +2789,7 @@
if (isUnary || N0 == N1) {
// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
// first operand.
- std::vector<SDOperand> MappedOps;
+ SmallVector<SDOperand, 8> MappedOps;
for (unsigned i = 0; i != NumElts; ++i) {
if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
@@ -2801,7 +2805,7 @@
MappedOps.push_back(ShufMask.getOperand(NumElts+1));
ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
- MappedOps);
+ &MappedOps[0], MappedOps.size());
AddToWorkList(ShufMask.Val);
// Build the undef vector.
@@ -2810,7 +2814,8 @@
MappedOps[i] = UDVal;
MappedOps[NumElts ] = *(N0.Val->op_end()-2);
MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
- UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
+ UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &MappedOps[0], MappedOps.size());
return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
N0, UDVal, ShufMask,
@@ -2863,13 +2868,16 @@
std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
ZeroOps.push_back(NumEltsNode);
ZeroOps.push_back(EVTNode);
- Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
+ Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &ZeroOps[0], ZeroOps.size()));
IdxOps.push_back(NumEltsNode);
IdxOps.push_back(EVTNode);
- Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
+ Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &IdxOps[0], IdxOps.size()));
Ops.push_back(NumEltsNode);
Ops.push_back(EVTNode);
- SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
+ SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
+ &Ops[0], Ops.size());
if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
DstVecSize, DstVecEVT);
@@ -2896,7 +2904,7 @@
// this operation.
if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
RHS.getOpcode() == ISD::VBUILD_VECTOR) {
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
SDOperand LHSOp = LHS.getOperand(i);
SDOperand RHSOp = RHS.getOperand(i);
@@ -2927,7 +2935,7 @@
if (Ops.size() == LHS.getNumOperands()-2) {
Ops.push_back(*(LHS.Val->op_end()-2));
Ops.push_back(*(LHS.Val->op_end()-1));
- return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
}
}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.385 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.386
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.385 Mon Aug 7 20:09:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Aug 7 21:23:41 2006
@@ -241,7 +241,7 @@
assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
if (NumEltsGrowth > 1) {
// Renumber the elements.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
SDOperand InOp = Mask.getOperand(i);
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
@@ -253,7 +253,7 @@
}
}
}
- Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
}
VT = NVT;
break;
@@ -666,7 +666,7 @@
cast<StringSDNode>(Node->getOperand(4))->getValue();
unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
Ops.push_back(Tmp1); // chain
SDOperand LineOp = Node->getOperand(1);
SDOperand ColOp = Node->getOperand(2);
@@ -675,13 +675,13 @@
Ops.push_back(LineOp); // line #
Ops.push_back(ColOp); // col #
Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
- Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+ Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
} else {
unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
+ Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
}
} else {
Result = Tmp1; // chain
@@ -889,14 +889,15 @@
// We generate a shuffle of InVec and ScVec, so the shuffle mask should
// be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
// the RHS.
- std::vector<SDOperand> ShufOps;
+ SmallVector<SDOperand, 8> ShufOps;
for (unsigned i = 0; i != NumElts; ++i) {
if (i != InsertPos->getValue())
ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
else
ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
}
- SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
+ SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
+ &ShufOps[0], ShufOps.size());
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
Tmp1, ScVec, ShufMask);
@@ -985,7 +986,7 @@
MVT::ValueType PtrVT = TLI.getPointerTy();
SDOperand Mask = Node->getOperand(2);
unsigned NumElems = Mask.getNumOperands();
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand,8> Ops;
for (unsigned i = 0; i != NumElems; ++i) {
SDOperand Arg = Mask.getOperand(i);
if (Arg.getOpcode() == ISD::UNDEF) {
@@ -1001,7 +1002,7 @@
DAG.getConstant(Idx - NumElems, PtrVT)));
}
}
- Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+ Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
break;
}
case TargetLowering::Promote: {
@@ -2149,7 +2150,7 @@
assert(MVT::isVector(Node->getValueType(0)) &&
"Cannot expand this binary operator!");
// Expand the operation into a bunch of nasty scalar code.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
MVT::ValueType PtrVT = TLI.getPointerTy();
for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
@@ -2159,7 +2160,8 @@
SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
}
- Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
+ Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
+ &Ops[0], Ops.size());
break;
}
case TargetLowering::Promote: {
@@ -3556,7 +3558,8 @@
MVT::getIntVectorWithNumElements(NumElems);
SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
std::vector<SDOperand> ZeroVec(NumElems, Zero);
- SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
+ SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ &ZeroVec[0], ZeroVec.size());
// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
@@ -3586,12 +3589,13 @@
MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
i += NumElems;
}
- SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
+ SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
+ &MaskVec[0], MaskVec.size());
// If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
E = Values.end(); I != E; ++I) {
SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
@@ -3601,7 +3605,8 @@
Ops.push_back(ShuffleMask);
// Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
- return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
+ return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
+ &Ops[0], Ops.size());
}
}
@@ -3613,7 +3618,7 @@
SDOperand FIPtr = CreateStackTemporary(VT);
// Emit a store of each element to the stack slot.
- std::vector<SDOperand> Stores;
+ SmallVector<SDOperand, 8> Stores;
unsigned TypeByteSize =
MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
unsigned VectorSize = MVT::getSizeInBits(VT)/8;
@@ -3634,7 +3639,8 @@
SDOperand StoreChain;
if (!Stores.empty()) // Not all undef elements?
- StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+ StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
@@ -3658,12 +3664,9 @@
SDOperand LHSL, LHSH;
ExpandOp(Op, LHSL, LHSH);
- std::vector<SDOperand> Ops;
- Ops.push_back(LHSL);
- Ops.push_back(LHSH);
- Ops.push_back(Amt);
+ SDOperand Ops[] = { LHSL, LHSH, Amt };
std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
- Lo = DAG.getNode(NodeOp, VTs, Ops);
+ Lo = DAG.getNode(NodeOp, VTs, Ops, 3);
Hi = Lo.getValue(1);
}
@@ -4634,21 +4637,21 @@
ExpandOp(Node->getOperand(0), LHSL, LHSH);
ExpandOp(Node->getOperand(1), RHSL, RHSH);
std::vector<MVT::ValueType> VTs;
- std::vector<SDOperand> LoOps, HiOps;
+ SDOperand LoOps[2], HiOps[2];
VTs.push_back(LHSL.getValueType());
VTs.push_back(MVT::Flag);
- LoOps.push_back(LHSL);
- LoOps.push_back(RHSL);
- HiOps.push_back(LHSH);
- HiOps.push_back(RHSH);
+ LoOps[0] = LHSL;
+ LoOps[1] = RHSL;
+ HiOps[0] = LHSH;
+ HiOps[1] = RHSH;
if (Node->getOpcode() == ISD::ADD) {
- Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
- HiOps.push_back(Lo.getValue(1));
- Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
+ Lo = DAG.getNode(ISD::ADDC, VTs, LoOps, 2);
+ HiOps[2] = Lo.getValue(1);
+ Hi = DAG.getNode(ISD::ADDE, VTs, HiOps, 3);
} else {
- Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
- HiOps.push_back(Lo.getValue(1));
- Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
+ Lo = DAG.getNode(ISD::SUBC, VTs, LoOps, 2);
+ HiOps[2] = Lo.getValue(1);
+ Hi = DAG.getNode(ISD::SUBE, VTs, HiOps, 3);
}
break;
}
@@ -4732,15 +4735,17 @@
#endif
assert(0 && "Unhandled operation in SplitVectorOp!");
case ISD::VBUILD_VECTOR: {
- std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
+ SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
+ Node->op_begin()+NewNumElts);
LoOps.push_back(NewNumEltsNode);
LoOps.push_back(TypeNode);
- Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
+ Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
- std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
+ SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
+ Node->op_end()-2);
HiOps.push_back(NewNumEltsNode);
HiOps.push_back(TypeNode);
- Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
+ Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
break;
}
case ISD::VADD:
@@ -4891,8 +4896,8 @@
if (AllUndef) {
Result = DAG.getNode(ISD::UNDEF, NewVT);
} else {
- std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
- Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
+ Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
+ Node->getNumOperands()-2);
}
}
break;
@@ -4920,7 +4925,9 @@
std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
Node->getOperand(2).Val->op_end()-2);
MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
- SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
+ SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
+ Node->getOperand(2).Val->op_begin(),
+ Node->getOperand(2).Val->getNumOperands()-2);
Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
PackVectorOp(Node->getOperand(0), NewVT),
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.320 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.321
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.320 Mon Aug 7 20:09:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Aug 7 21:23:41 2006
@@ -1539,16 +1539,11 @@
SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT,
SDOperand Chain, SDOperand Ptr, SDOperand SV,
MVT::ValueType EVT) {
- std::vector<SDOperand> Ops;
- Ops.reserve(4);
- Ops.push_back(Chain);
- Ops.push_back(Ptr);
- Ops.push_back(SV);
- Ops.push_back(getValueType(EVT));
+ SDOperand Ops[] = { Chain, Ptr, SV, getValueType(EVT) };
std::vector<MVT::ValueType> VTs;
VTs.reserve(2);
VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain.
- return getNode(Opcode, VTs, Ops);
+ return getNode(Opcode, VTs, Ops, 4);
}
SDOperand SelectionDAG::getSrcValue(const Value *V, int Offset) {
@@ -1565,15 +1560,11 @@
SDOperand SelectionDAG::getVAArg(MVT::ValueType VT,
SDOperand Chain, SDOperand Ptr,
SDOperand SV) {
- std::vector<SDOperand> Ops;
- Ops.reserve(3);
- Ops.push_back(Chain);
- Ops.push_back(Ptr);
- Ops.push_back(SV);
+ SDOperand Ops[] = { Chain, Ptr, SV };
std::vector<MVT::ValueType> VTs;
VTs.reserve(2);
VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain.
- return getNode(ISD::VAARG, VTs, Ops);
+ return getNode(ISD::VAARG, VTs, Ops, 3);
}
SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
@@ -1719,17 +1710,6 @@
return SDOperand(N, 0);
}
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
- std::vector<SDOperand> &Ops) {
- return getNode(Opcode, VT, &Ops[0], Ops.size());
-}
-
-SDOperand SelectionDAG::getNode(unsigned Opcode,
- std::vector<MVT::ValueType> &ResultTys,
- std::vector<SDOperand> &Ops) {
- return getNode(Opcode, ResultTys, &Ops[0], Ops.size());
-}
-
MVT::ValueType *SelectionDAG::getNodeValueTypes(MVT::ValueType VT) {
return SDNode::getValueTypeList(VT);
@@ -2233,59 +2213,33 @@
SDOperand Op1, SDOperand Op2, SDOperand Op3,
SDOperand Op4, SDOperand Op5,
SDOperand Op6) {
- std::vector<SDOperand> Ops;
- Ops.reserve(6);
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 6).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3,
SDOperand Op4, SDOperand Op5, SDOperand Op6,
SDOperand Op7) {
- std::vector<SDOperand> Ops;
- Ops.reserve(7);
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- Ops.push_back(Op7);
- return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 7).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
SDOperand Op1, SDOperand Op2, SDOperand Op3,
SDOperand Op4, SDOperand Op5, SDOperand Op6,
SDOperand Op7, SDOperand Op8) {
- std::vector<SDOperand> Ops;
- Ops.reserve(8);
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- Ops.push_back(Op7);
- Ops.push_back(Op8);
- return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, 8).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT,
- std::vector<SDOperand> &Ops) {
- return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops).Val;
+ const SDOperand *Ops, unsigned NumOps) {
+ return getNode(ISD::BUILTIN_OP_END+Opcode, VT, Ops, NumOps).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1) {
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, &Op1, 1).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1,
@@ -2293,10 +2247,8 @@
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 2).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1,
@@ -2304,11 +2256,8 @@
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 3).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1,
@@ -2317,12 +2266,8 @@
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 4).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1,
@@ -2331,13 +2276,8 @@
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 5).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1,
@@ -2346,14 +2286,8 @@
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 6).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, SDOperand Op1,
@@ -2363,15 +2297,8 @@
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- Ops.push_back(Op7);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 7).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2380,10 +2307,8 @@
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
ResultTys.push_back(VT3);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 2).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2394,13 +2319,8 @@
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
ResultTys.push_back(VT3);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 5).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2411,14 +2331,8 @@
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
ResultTys.push_back(VT3);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 6).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2, MVT::ValueType VT3,
@@ -2429,23 +2343,16 @@
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
ResultTys.push_back(VT3);
- std::vector<SDOperand> Ops;
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- Ops.push_back(Op5);
- Ops.push_back(Op6);
- Ops.push_back(Op7);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ SDOperand Ops[] = { Op1, Op2, Op3, Op4, Op5, Op6, Op7 };
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, 7).Val;
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, MVT::ValueType VT1,
MVT::ValueType VT2,
- std::vector<SDOperand> &Ops) {
+ const SDOperand *Ops, unsigned NumOps) {
std::vector<MVT::ValueType> ResultTys;
ResultTys.push_back(VT1);
ResultTys.push_back(VT2);
- return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops).Val;
+ return getNode(ISD::BUILTIN_OP_END+Opcode, ResultTys, Ops, NumOps).Val;
}
/// ReplaceAllUsesWith - Modify anything using 'From' to use 'To' instead.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.267 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.268
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.267 Wed Aug 2 19:18:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Aug 7 21:23:41 2006
@@ -437,7 +437,8 @@
}
// Otherwise, we have to make a token factor node.
- SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other, PendingLoads);
+ SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
return Root;
@@ -598,13 +599,14 @@
unsigned NumElements = PTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
// Create a VConstant node with generic Vector type.
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
Ops.push_back(DAG.getValueType(PVT));
- return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
+ &Ops[0], Ops.size());
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
return N = DAG.getConstantFP(CFP->getValue(), VT);
} else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
@@ -614,7 +616,7 @@
// Now that we know the number and type of the elements, push a
// Constant or ConstantFP node onto the ops list for each element of
// the packed constant.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
for (unsigned i = 0; i != NumElements; ++i)
Ops.push_back(getValue(CP->getOperand(i)));
@@ -631,7 +633,7 @@
// Create a VBUILD_VECTOR node with generic Vector type.
Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
Ops.push_back(DAG.getValueType(PVT));
- return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
} else {
// Canonicalize all constant ints to be unsigned.
return N = DAG.getConstant(cast<ConstantIntegral>(C)->getRawValue(),VT);
@@ -676,7 +678,7 @@
PTyLegalElementVT);
// Build a VBUILD_VECTOR with the input registers.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
if (PTyElementVT == PTyLegalElementVT) {
// If the value types are legal, just VBUILD the CopyFromReg nodes.
for (unsigned i = 0; i != NE; ++i)
@@ -707,7 +709,7 @@
Ops.push_back(DAG.getConstant(NE, MVT::i32));
Ops.push_back(DAG.getValueType(PTyLegalElementVT));
- N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
// Finally, use a VBIT_CONVERT to make this available as the appropriate
// vector type.
@@ -726,7 +728,7 @@
DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
return;
}
- std::vector<SDOperand> NewValues;
+ SmallVector<SDOperand, 8> NewValues;
NewValues.push_back(getRoot());
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
SDOperand RetOp = getValue(I.getOperand(i));
@@ -753,7 +755,8 @@
NewValues.push_back(RetOp);
NewValues.push_back(DAG.getConstant(isSigned, MVT::i32));
}
- DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, NewValues));
+ DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
+ &NewValues[0], NewValues.size()));
}
void SelectionDAGLowering::visitBr(BranchInst &I) {
@@ -1346,11 +1349,8 @@
std::vector<MVT::ValueType> VTs;
VTs.push_back(AllocSize.getValueType());
VTs.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- Ops.push_back(AllocSize);
- Ops.push_back(getIntPtrConstant(Align));
- SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
+ SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
+ SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops, 3);
DAG.setRoot(setValue(&I, DSA).getValue(1));
// Inform the Frame Information that we have just allocated a variable-sized
@@ -1427,7 +1427,7 @@
bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
// Build the operand list.
- std::vector<SDOperand> Ops;
+ SmallVector<SDOperand, 8> Ops;
if (HasChain) { // If this intrinsic has side-effects, chainify it.
if (OnlyLoad) {
// We don't need to serialize loads against other loads.
@@ -1479,11 +1479,11 @@
// Create the node.
SDOperand Result;
if (!HasChain)
- Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, Ops);
+ Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTs, &Ops[0], Ops.size());
else if (I.getType() != Type::VoidTy)
- Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, Ops);
+ Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTs, &Ops[0], Ops.size());
else
- Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, Ops);
+ Result = DAG.getNode(ISD::INTRINSIC_VOID, VTs, &Ops[0], Ops.size());
if (HasChain) {
SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
@@ -1541,20 +1541,20 @@
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
- std::vector<SDOperand> Ops;
+ SDOperand Ops[5];
- Ops.push_back(getRoot());
- Ops.push_back(getValue(SPI.getLineValue()));
- Ops.push_back(getValue(SPI.getColumnValue()));
+ Ops[0] = getRoot();
+ Ops[1] = getValue(SPI.getLineValue());
+ Ops[2] = getValue(SPI.getColumnValue());
DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
assert(DD && "Not a debug information descriptor");
CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
- Ops.push_back(DAG.getString(CompileUnit->getFileName()));
- Ops.push_back(DAG.getString(CompileUnit->getDirectory()));
+ Ops[3] = DAG.getString(CompileUnit->getFileName());
+ Ops[4] = DAG.getString(CompileUnit->getDirectory());
- DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
}
return 0;
@@ -1563,14 +1563,9 @@
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
- std::vector<SDOperand> Ops;
-
unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
-
- Ops.push_back(getRoot());
- Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
+ DAG.getConstant(LabelID, MVT::i32)));
}
return 0;
@@ -1579,14 +1574,9 @@
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
- std::vector<SDOperand> Ops;
-
unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
-
- Ops.push_back(getRoot());
- Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
return 0;
@@ -1596,14 +1586,9 @@
DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
if (DebugInfo && FSI.getSubprogram() &&
DebugInfo->Verify(FSI.getSubprogram())) {
- std::vector<SDOperand> Ops;
-
unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
-
- Ops.push_back(getRoot());
- Ops.push_back(DAG.getConstant(LabelID, MVT::i32));
-
- DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
+ getRoot(), DAG.getConstant(LabelID, MVT::i32)));
}
return 0;
@@ -1612,12 +1597,9 @@
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
- std::vector<SDOperand> Ops;
-
SDOperand AddressOp = getValue(DI.getAddress());
- if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp)) {
+ if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
- }
}
return 0;
@@ -1644,9 +1626,8 @@
std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i64);
VTs.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, Ops);
+ SDOperand Op = getRoot();
+ SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER, VTs, &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
@@ -1686,9 +1667,8 @@
std::vector<MVT::ValueType> VTs;
VTs.push_back(TLI.getPointerTy());
VTs.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, Ops);
+ SDOperand Op = getRoot();
+ SDOperand Tmp = DAG.getNode(ISD::STACKSAVE, VTs, &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
@@ -2279,7 +2259,8 @@
std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::Other);
VTs.push_back(MVT::Flag);
- Chain = DAG.getNode(ISD::INLINEASM, VTs, AsmNodeOperands);
+ Chain = DAG.getNode(ISD::INLINEASM, VTs,
+ &AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
// If this asm returns a register value, copy the result from that register
@@ -2299,14 +2280,15 @@
}
// Emit the non-flagged stores from the physregs.
- std::vector<SDOperand> OutChains;
+ SmallVector<SDOperand, 8> OutChains;
for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
StoresToEmit[i].first,
getValue(StoresToEmit[i].second),
DAG.getSrcValue(StoresToEmit[i].second)));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
@@ -2446,7 +2428,8 @@
RetVals.push_back(MVT::Other);
// Create the node.
- SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals, Ops).Val;
+ SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS, RetVals,
+ &Ops[0], Ops.size()).Val;
DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
@@ -2653,7 +2636,7 @@
RetTys.push_back(MVT::Other); // Always has a chain.
// Finally, create the CALL node.
- SDOperand Res = DAG.getNode(ISD::CALL, RetTys, Ops);
+ SDOperand Res = DAG.getNode(ISD::CALL, RetTys, &Ops[0], Ops.size());
// This returns a pair of operands. The first element is the
// return value for the function (if RetTy is not VoidTy). The second
@@ -2862,7 +2845,7 @@
// Expand memset / memcpy to a series of load / store ops
// if the size operand falls below a certain threshold.
- std::vector<SDOperand> OutChains;
+ SmallVector<SDOperand, 8> OutChains;
switch (Op) {
default: break; // Do nothing for now.
case ISD::MEMSET: {
@@ -2944,18 +2927,13 @@
}
if (!OutChains.empty()) {
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size()));
return;
}
}
- std::vector<SDOperand> Ops;
- Ops.push_back(getRoot());
- Ops.push_back(Op1);
- Ops.push_back(Op2);
- Ops.push_back(Op3);
- Ops.push_back(Op4);
- DAG.setRoot(DAG.getNode(Op, MVT::Other, Ops));
+ DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
}
//===----------------------------------------------------------------------===//
@@ -3318,7 +3296,7 @@
// Loop over all of the elements of the resultant vector,
// VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
// copying them into output registers.
- std::vector<SDOperand> OutChains;
+ SmallVector<SDOperand, 8> OutChains;
SDOperand Root = SDL.getRoot();
for (unsigned i = 0; i != NE; ++i) {
SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
@@ -3344,7 +3322,8 @@
OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
}
}
- return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains);
+ return DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size());
} else if (SrcVT < DestVT) {
// The src value is promoted to the register.
if (MVT::isFloatingPoint(SrcVT))
@@ -3500,7 +3479,8 @@
if (i == e)
UnorderedChains.push_back(Root);
}
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, UnorderedChains));
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &UnorderedChains[0], UnorderedChains.size()));
}
// Lower the terminator after the copies are emitted.
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