[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.4 -> 1.5
ARMISelDAGToDAG.cpp updated: 1.14 -> 1.15
ARMInstrInfo.td updated: 1.6 -> 1.7
ARMRegisterInfo.cpp updated: 1.6 -> 1.7
---
Log message:

add the memri memory operand
this makes it possible for ldr instructions with non-zero immediate


---
Diffs of the changes:  (+42 -14)

 ARMAsmPrinter.cpp   |    6 ++++++
 ARMISelDAGToDAG.cpp |    7 +++++--
 ARMInstrInfo.td     |   17 +++++++++++++----
 ARMRegisterInfo.cpp |   26 ++++++++++++++++++--------
 4 files changed, 42 insertions(+), 14 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.4 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.5
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.4	Fri May 26 05:56:17 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Tue Jul 11 06:36:48 2006
@@ -58,6 +58,12 @@
       return "ARM Assembly Printer";
     }
 
+    void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
+      printOperand(MI, OpNo + 1);
+      O << ", ";
+      printOperand(MI, OpNo);
+    }
+
     void printOperand(const MachineInstr *MI, int opNum);
     void printMemOperand(const MachineInstr *MI, int opNum,
                          const char *Modifier = 0);


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.14 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.15
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.14	Sun Jul  9 20:41:35 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Tue Jul 11 06:36:48 2006
@@ -164,7 +164,7 @@
 
   void Select(SDOperand &Result, SDOperand Op);
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
-  bool SelectAddrReg(SDOperand N, SDOperand &Base);
+  bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
 
   // Include the pieces autogenerated from the target description.
 #include "ARMGenDAGISel.inc"
@@ -183,7 +183,10 @@
   ScheduleAndEmitDAG(DAG);
 }
 
-bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) {
+//register plus/minus 12 bit offset
+bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
+				    SDOperand &Base) {
+  Offset = CurDAG->getTargetConstant(0, MVT::i32);
   if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
     Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
   }


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.6 llvm/lib/Target/ARM/ARMInstrInfo.td:1.7
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.6	Sun Jul  9 20:41:35 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Jul 11 06:36:48 2006
@@ -12,9 +12,18 @@
 //
 //===----------------------------------------------------------------------===//
 
+// Address operands
+def memri : Operand<iPTR> {
+  let PrintMethod = "printMemRegImm";
+  let NumMIOperands = 2;
+  let MIOperandInfo = (ops i32imm, ptr_rc);
+}
+
 // Define ARM specific addressing mode.
- //register or frame index
-def raddr  : ComplexPattern<iPTR, 1, "SelectAddrReg", []>;
+//register plus/minus 12 bit offset
+def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrRegImm", []>;
+//register plus scaled register
+//def raddr  : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -42,9 +51,9 @@
 
 def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
 
-def ldr   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
                      "ldr $dst, [$addr]",
-                     [(set IntRegs:$dst, (load raddr:$addr))]>;
+                     [(set IntRegs:$dst, (load iaddr:$addr))]>;
 
 def str  : InstARM<(ops IntRegs:$src, IntRegs:$addr),
                     "str $src, [$addr]",


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.6 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.7
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.6	Sun Jul  9 20:41:35 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Tue Jul 11 06:36:48 2006
@@ -83,23 +83,33 @@
 
   assert (MI.getOpcode() == ARM::ldr);
 
-  unsigned FrameIdx = 1;
+  unsigned FrameIdx = 2;
+  unsigned OffIdx = 1;
 
   int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
 
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
+  assert (MI.getOperand(OffIdx).getImmedValue() == 0);
 
   unsigned StackSize = MF.getFrameInfo()->getStackSize();
 
   Offset += StackSize;
 
-  // Insert a set of r12 with the full address
-  // r12 = r13 + offset
-  MachineBasicBlock *MBB2 = MI.getParent();
-  BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
-
-  // Replace the FrameIndex with r12
-  MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
+  assert (Offset >= 0);
+  if (Offset < 4096) {
+    // Replace the FrameIndex with r13
+    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
+    // Replace the ldr offset with Offset
+    MI.getOperand(OffIdx).ChangeToImmediate(Offset);
+  } else {
+    // Insert a set of r12 with the full address
+    // r12 = r13 + offset
+    MachineBasicBlock *MBB2 = MI.getParent();
+    BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
+
+    // Replace the FrameIndex with r12
+    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
+  }
 }
 
 void ARMRegisterInfo::