[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.td X86RegisterInfo.cpp
Evan Cheng
evan.cheng at apple.com
Wed Jun 28 17:37:03 PDT 2006
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.td updated: 1.277 -> 1.278
X86RegisterInfo.cpp updated: 1.158 -> 1.159
---
Log message:
Add shift and rotate by 1 instructions / patterns.
---
Diffs of the changes: (+128 -0)
X86InstrInfo.td | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++
X86RegisterInfo.cpp | 15 ++++++
2 files changed, 128 insertions(+)
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.277 llvm/lib/Target/X86/X86InstrInfo.td:1.278
--- llvm/lib/Target/X86/X86InstrInfo.td:1.277 Tue Jun 27 15:34:14 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td Wed Jun 28 19:36:51 2006
@@ -1394,6 +1394,14 @@
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
}
+// Shift left by one. Not used because (add x, x) is slightly cheaper.
+def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
+ "shl{b} {$dst|$dst}", []>;
+def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
+ "shl{w} {$dst|$dst}", []>, OpSize;
+def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
+ "shl{l} {$dst|$dst}", []>;
+
let isTwoAddress = 0 in {
def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
"shl{b} {%cl, $dst|$dst, %CL}",
@@ -1417,6 +1425,18 @@
def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
"shl{l} {$src, $dst|$dst, $src}",
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Shift by 1
+ def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
+ "shl{b} $dst",
+ [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
+ "shl{w} $dst",
+ [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
+ "shl{l} $dst",
+ [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
@@ -1439,6 +1459,17 @@
"shr{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
+// Shift by 1
+def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
+ "shr{b} $dst",
+ [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
+def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
+ "shr{w} $dst",
+ [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
+def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
+ "shr{l} $dst",
+ [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
"shr{b} {%cl, $dst|$dst, %CL}",
@@ -1462,6 +1493,17 @@
def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
"shr{l} {$src, $dst|$dst, $src}",
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Shift by 1
+ def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
+ "shr{b} $dst",
+ [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
+ "shr{w} $dst",
+ [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
+ def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
+ "shr{l} $dst",
+ [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
@@ -1484,6 +1526,18 @@
def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
"sar{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
+
+// Shift by 1
+def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
+ "sar{b} $dst",
+ [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
+def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
+ "sar{w} $dst",
+ [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
+def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
+ "sar{l} $dst",
+ [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
"sar{b} {%cl, $dst|$dst, %CL}",
@@ -1507,6 +1561,18 @@
def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
"sar{l} {$src, $dst|$dst, $src}",
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Shift by 1
+ def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
+ "sar{b} $dst",
+ [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
+ "sar{w} $dst",
+ [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
+ "sar{l} $dst",
+ [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
// Rotate instructions
@@ -1531,6 +1597,17 @@
"rol{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
+// Rotate by 1
+def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
+ "rol{b} $dst",
+ [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
+def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
+ "rol{w} $dst",
+ [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
+def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
+ "rol{l} $dst",
+ [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
"rol{b} {%cl, $dst|$dst, %CL}",
@@ -1554,6 +1631,18 @@
def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
"rol{l} {$src, $dst|$dst, $src}",
[(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Rotate by 1
+ def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
+ "rol{b} $dst",
+ [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
+ "rol{w} $dst",
+ [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
+ "rol{l} $dst",
+ [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
@@ -1575,6 +1664,18 @@
def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
"ror{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
+
+// Rotate by 1
+def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
+ "ror{b} $dst",
+ [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
+def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
+ "ror{w} $dst",
+ [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
+def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
+ "ror{l} $dst",
+ [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
+
let isTwoAddress = 0 in {
def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
"ror{b} {%cl, $dst|$dst, %CL}",
@@ -1598,6 +1699,18 @@
def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
"ror{l} {$src, $dst|$dst, $src}",
[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
+
+ // Rotate by 1
+ def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
+ "ror{b} $dst",
+ [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
+ def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
+ "ror{w} $dst",
+ [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
+ OpSize;
+ def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
+ "ror{l} $dst",
+ [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
}
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.158 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.159
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.158 Tue Jun 13 00:14:44 2006
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jun 28 19:36:51 2006
@@ -288,30 +288,45 @@
case X86::SHL8ri: return MakeMIInst(X86::SHL8mi , FrameIndex, MI);
case X86::SHL16ri: return MakeMIInst(X86::SHL16mi, FrameIndex, MI);
case X86::SHL32ri: return MakeMIInst(X86::SHL32mi, FrameIndex, MI);
+ case X86::SHL8r1: return MakeMInst(X86::SHL8m1 , FrameIndex, MI);
+ case X86::SHL16r1: return MakeMInst(X86::SHL16m1, FrameIndex, MI);
+ case X86::SHL32r1: return MakeMInst(X86::SHL32m1, FrameIndex, MI);
case X86::SHR8rCL: return MakeMInst( X86::SHR8mCL ,FrameIndex, MI);
case X86::SHR16rCL: return MakeMInst( X86::SHR16mCL,FrameIndex, MI);
case X86::SHR32rCL: return MakeMInst( X86::SHR32mCL,FrameIndex, MI);
case X86::SHR8ri: return MakeMIInst(X86::SHR8mi , FrameIndex, MI);
case X86::SHR16ri: return MakeMIInst(X86::SHR16mi, FrameIndex, MI);
case X86::SHR32ri: return MakeMIInst(X86::SHR32mi, FrameIndex, MI);
+ case X86::SHR8r1: return MakeMInst(X86::SHR8m1 , FrameIndex, MI);
+ case X86::SHR16r1: return MakeMInst(X86::SHR16m1, FrameIndex, MI);
+ case X86::SHR32r1: return MakeMInst(X86::SHR32m1, FrameIndex, MI);
case X86::SAR8rCL: return MakeMInst( X86::SAR8mCL ,FrameIndex, MI);
case X86::SAR16rCL: return MakeMInst( X86::SAR16mCL,FrameIndex, MI);
case X86::SAR32rCL: return MakeMInst( X86::SAR32mCL,FrameIndex, MI);
case X86::SAR8ri: return MakeMIInst(X86::SAR8mi , FrameIndex, MI);
case X86::SAR16ri: return MakeMIInst(X86::SAR16mi, FrameIndex, MI);
case X86::SAR32ri: return MakeMIInst(X86::SAR32mi, FrameIndex, MI);
+ case X86::SAR8r1: return MakeMInst(X86::SAR8m1 , FrameIndex, MI);
+ case X86::SAR16r1: return MakeMInst(X86::SAR16m1, FrameIndex, MI);
+ case X86::SAR32r1: return MakeMInst(X86::SAR32m1, FrameIndex, MI);
case X86::ROL8rCL: return MakeMInst( X86::ROL8mCL ,FrameIndex, MI);
case X86::ROL16rCL: return MakeMInst( X86::ROL16mCL,FrameIndex, MI);
case X86::ROL32rCL: return MakeMInst( X86::ROL32mCL,FrameIndex, MI);
case X86::ROL8ri: return MakeMIInst(X86::ROL8mi , FrameIndex, MI);
case X86::ROL16ri: return MakeMIInst(X86::ROL16mi, FrameIndex, MI);
case X86::ROL32ri: return MakeMIInst(X86::ROL32mi, FrameIndex, MI);
+ case X86::ROL8r1: return MakeMInst(X86::ROL8m1 , FrameIndex, MI);
+ case X86::ROL16r1: return MakeMInst(X86::ROL16m1, FrameIndex, MI);
+ case X86::ROL32r1: return MakeMInst(X86::ROL32m1, FrameIndex, MI);
case X86::ROR8rCL: return MakeMInst( X86::ROR8mCL ,FrameIndex, MI);
case X86::ROR16rCL: return MakeMInst( X86::ROR16mCL,FrameIndex, MI);
case X86::ROR32rCL: return MakeMInst( X86::ROR32mCL,FrameIndex, MI);
case X86::ROR8ri: return MakeMIInst(X86::ROR8mi , FrameIndex, MI);
case X86::ROR16ri: return MakeMIInst(X86::ROR16mi, FrameIndex, MI);
case X86::ROR32ri: return MakeMIInst(X86::ROR32mi, FrameIndex, MI);
+ case X86::ROR8r1: return MakeMInst(X86::ROR8m1 , FrameIndex, MI);
+ case X86::ROR16r1: return MakeMInst(X86::ROR16m1, FrameIndex, MI);
+ case X86::ROR32r1: return MakeMInst(X86::ROR32m1, FrameIndex, MI);
case X86::SHLD32rrCL:return MakeMRInst( X86::SHLD32mrCL,FrameIndex, MI);
case X86::SHLD32rri8:return MakeMRIInst(X86::SHLD32mri8,FrameIndex, MI);
case X86::SHRD32rrCL:return MakeMRInst( X86::SHRD32mrCL,FrameIndex, MI);
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