[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Chris Lattner
lattner at cs.uiuc.edu
Tue Jun 20 17:34:16 PDT 2006
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.190 -> 1.191
---
Log message:
Correct returns of 64-bit values, though they seemed to work before...
---
Diffs of the changes: (+19 -9)
PPCISelLowering.cpp | 28 +++++++++++++++++++---------
1 files changed, 19 insertions(+), 9 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.190 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.191
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.190 Fri Jun 16 16:01:35 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 20 19:34:03 2006
@@ -733,8 +733,8 @@
Op.getOperand(1), Op.getOperand(2));
}
-static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
- int &VarArgsFrameIndex) {
+static SDOperand LowerFORMAL_ARGUMENTS_32(SDOperand Op, SelectionDAG &DAG,
+ int &VarArgsFrameIndex) {
// TODO: add description of PPC stack frame format, or at least some docs.
//
MachineFunction &MF = DAG.getMachineFunction();
@@ -883,6 +883,11 @@
return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
}
+static SDOperand LowerFORMAL_ARGUMENTS_64(SDOperand Op, SelectionDAG &DAG,
+ int &VarArgsFrameIndex) {
+ return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
+}
+
/// isCallCompatibleAddress - Return the immediate to use if the specified
/// 32-bit value is representable in the immediate field of a BxA instruction.
static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
@@ -1165,13 +1170,15 @@
case 3: {
MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
unsigned ArgReg;
- if (MVT::isVector(ArgVT))
- ArgReg = PPC::V2;
- else if (MVT::isInteger(ArgVT))
+ if (ArgVT == MVT::i32) {
ArgReg = PPC::R3;
- else {
- assert(MVT::isFloatingPoint(ArgVT));
+ } else if (ArgVT == MVT::i64) {
+ ArgReg = PPC::X3;
+ } else if (MVT::isFloatingPoint(ArgVT)) {
ArgReg = PPC::F1;
+ } else {
+ assert(MVT::isVector(ArgVT));
+ ArgReg = PPC::V2;
}
Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
@@ -2128,8 +2135,11 @@
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
- case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
- VarArgsFrameIndex);
+ case ISD::FORMAL_ARGUMENTS:
+ if (getPointerTy() == MVT::i32)
+ return LowerFORMAL_ARGUMENTS_32(Op, DAG, VarArgsFrameIndex);
+ else
+ return LowerFORMAL_ARGUMENTS_64(Op, DAG, VarArgsFrameIndex);
case ISD::CALL: return LowerCALL(Op, DAG);
case ISD::RET: return LowerRET(Op, DAG);
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