[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstr64Bit.td PPCInstrInfo.td

Chris Lattner lattner at cs.uiuc.edu
Tue Jun 20 15:34:33 PDT 2006



Changes in directory llvm/lib/Target/PowerPC:

PPCInstr64Bit.td updated: 1.5 -> 1.6
PPCInstrInfo.td updated: 1.227 -> 1.228
---
Log message:

Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr



---
Diffs of the changes:  (+78 -16)

 PPCInstr64Bit.td |   66 ++++++++++++++++++++++++++++++++++++++++++++++++-------
 PPCInstrInfo.td  |   28 ++++++++++++++++-------
 2 files changed, 78 insertions(+), 16 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.5 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.6
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.5	Tue Jun 20 16:23:06 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td	Tue Jun 20 17:34:10 2006
@@ -31,13 +31,7 @@
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 
-def LI8  : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
-                      "li $rD, $imm", IntGeneral,
-                      [(set G8RC:$rD, immSExt16:$imm)]>;
-def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
-                      "lis $rD, $imm", IntGeneral,
-                      [(set G8RC:$rD, imm16Shifted:$imm)]>;
-
+// Copies, extends, truncates.
 def OR8  : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
                    "or $rA, $rS, $rB", IntGeneral,
                    [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
@@ -47,13 +41,47 @@
 def OR8To4  : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
                    "or $rA, $rS, $rB", IntGeneral,
                    []>;
+
+def LI8  : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
+                      "li $rD, $imm", IntGeneral,
+                      [(set G8RC:$rD, immSExt16:$imm)]>;
+def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
+                      "lis $rD, $imm", IntGeneral,
+                      [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
+
+// Logical ops.
+def ANDIo8  : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+                      "andi. $dst, $src1, $src2", IntGeneral,
+                      [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
+                      isDOT;
+def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+                     "andis. $dst, $src1, $src2", IntGeneral,
+                    [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
+                     isDOT;
+def ORI8    : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+                      "ori $dst, $src1, $src2", IntGeneral,
+                      [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
+def ORIS8   : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+                      "oris $dst, $src1, $src2", IntGeneral,
+                    [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
+def XORI8   : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+                      "xori $dst, $src1, $src2", IntGeneral,
+                      [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
+def XORIS8  : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
+                      "xoris $dst, $src1, $src2", IntGeneral,
+                   [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
+
+
                    
 def ADD8  : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
                      "add $rT, $rA, $rB", IntGeneral,
                      [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
 def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
                      "addis $rD, $rA, $imm", IntGeneral,
-                     [(set G8RC:$rD, (add G8RC:$rA, imm16Shifted:$imm))]>;
+                     [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
+
+
+
 
 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
                      "mulhd $rT, $rA, $rB", IntMulHW,
@@ -186,6 +214,28 @@
 //===----------------------------------------------------------------------===//
 // Instruction Patterns
 //
+
+// Immediate support.
+// Handled above:
+//   sext(0x0000_0000_0000_FFFF,  i8) -> li imm
+//   sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16
+
+// sext(0x0000_0000_FFFF_FFFF,  i16)  -> lis + ori
+def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
+  return N->getValue() == (uint64_t)(int32_t)N->getValue();
+}]>;
+def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm),
+          (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>;
+
+// zext(0x0000_0000_FFFF_FFFF, i16) -> xoris (li lo16(imm)), imm>>16
+def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
+  return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0;
+}]>;
+def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm),
+          (XORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>;
+
+
+
 // Extensions and truncates to/from 32-bit regs.
 def : Pat<(i64 (zext GPRC:$in)),
           (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.227 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.228
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.227	Tue Jun 20 16:39:30 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Tue Jun 20 17:34:10 2006
@@ -140,9 +140,21 @@
   return (unsigned)N->getValue() == (unsigned short)N->getValue();
 }], LO16>;
 
-def imm16Shifted : PatLeaf<(imm), [{
-  // imm16Shifted predicate - True if only bits in the top 16-bits of the
-  // immediate are set.  Used by instructions like 'addis'.
+// imm16Shifted* - These match immediates where the low 16-bits are zero.  There
+// are two forms: imm16ShiftedSExt and imm16ShiftedZExt.  These two forms are
+// identical in 32-bit mode, but in 64-bit mode, they return true if the
+// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
+// clear).
+def imm16ShiftedZExt : PatLeaf<(imm), [{
+  // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
+  // immediate are set.  Used by instructions like 'xoris'.
+  return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
+}], HI16>;
+
+def imm16ShiftedSExt : PatLeaf<(imm), [{
+  // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
+  // immediate are set.  Used by instructions like 'addis'.  Identical to 
+  // imm16ShiftedZExt in 32-bit mode.
   if (N->getValue() & 0xFFFF) return false;
   if (N->getValueType(0) == MVT::i32)
     return true;
@@ -364,7 +376,7 @@
                      []>;
 def ADDIS  : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
                      "addis $rD, $rA, $imm", IntGeneral,
-                     [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
+                     [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
 def LA     : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
                      "la $rD, $sym($rA)", IntGeneral,
                      [(set GPRC:$rD, (add GPRC:$rA,
@@ -380,7 +392,7 @@
                      [(set GPRC:$rD, immSExt16:$imm)]>;
 def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
                      "lis $rD, $imm", IntGeneral,
-                     [(set GPRC:$rD, imm16Shifted:$imm)]>;
+                     [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
 }
 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
 def STB  : DForm_3<38, (ops GPRC:$rS, memri:$src),
@@ -403,20 +415,20 @@
                     isDOT;
 def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                     "andis. $dst, $src1, $src2", IntGeneral,
-                    [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
+                    [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
                     isDOT;
 def ORI   : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                     "ori $dst, $src1, $src2", IntGeneral,
                     [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
 def ORIS  : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                     "oris $dst, $src1, $src2", IntGeneral,
-                    [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
+                    [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
 def XORI  : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                     "xori $dst, $src1, $src2", IntGeneral,
                     [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
 def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
                     "xoris $dst, $src1, $src2", IntGeneral,
-                    [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
+                    [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
 def NOP   : DForm_4_zero<24, (ops), "nop", IntGeneral,
                          []>;
 def CMPI  : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),






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