[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.187 -> 1.188
---
Log message:

Type of extract_element index operand should be iPTR.

---
Diffs of the changes:  (+15 -12)

 PPCISelLowering.cpp |   27 +++++++++++++++------------
 1 files changed, 15 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.187 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.188
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.187	Fri Jun  9 20:14:28 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Thu Jun 15 03:17:07 2006
@@ -1334,7 +1334,8 @@
   return FP;
 }
 
-static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) {
+static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG,
+                          MVT::ValueType PtrVT) {
   assert(Op.getValueType() == MVT::i64 &&
          Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
   // The generic code does a fine job expanding shift by a constant.
@@ -1343,9 +1344,9 @@
   // Otherwise, expand into a bunch of logical ops.  Note that these ops
   // depend on the PPC behavior for oversized shift amounts.
   SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
-                             DAG.getConstant(0, MVT::i32));
+                             DAG.getConstant(0, PtrVT));
   SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
-                             DAG.getConstant(1, MVT::i32));
+                             DAG.getConstant(1, PtrVT));
   SDOperand Amt = Op.getOperand(1);
   
   SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
@@ -1361,7 +1362,8 @@
   return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
 }
 
-static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) {
+static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG,
+                          MVT::ValueType PtrVT) {
   assert(Op.getValueType() == MVT::i64 &&
          Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
   // The generic code does a fine job expanding shift by a constant.
@@ -1370,9 +1372,9 @@
   // Otherwise, expand into a bunch of logical ops.  Note that these ops
   // depend on the PPC behavior for oversized shift amounts.
   SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
-                             DAG.getConstant(0, MVT::i32));
+                             DAG.getConstant(0, PtrVT));
   SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
-                             DAG.getConstant(1, MVT::i32));
+                             DAG.getConstant(1, PtrVT));
   SDOperand Amt = Op.getOperand(1);
   
   SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
@@ -1388,7 +1390,8 @@
   return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
 }
 
-static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) {
+static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG,
+                          MVT::ValueType PtrVT) {
   assert(Op.getValueType() == MVT::i64 &&
          Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
   // The generic code does a fine job expanding shift by a constant.
@@ -1396,9 +1399,9 @@
   
   // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
   SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
-                             DAG.getConstant(0, MVT::i32));
+                             DAG.getConstant(0, PtrVT));
   SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
-                             DAG.getConstant(1, MVT::i32));
+                             DAG.getConstant(1, PtrVT));
   SDOperand Amt = Op.getOperand(1);
   
   SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
@@ -2132,9 +2135,9 @@
   case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
 
   // Lower 64-bit shifts.
-  case ISD::SHL:                return LowerSHL(Op, DAG);
-  case ISD::SRL:                return LowerSRL(Op, DAG);
-  case ISD::SRA:                return LowerSRA(Op, DAG);
+  case ISD::SHL:                return LowerSHL(Op, DAG, getPointerTy());
+  case ISD::SRL:                return LowerSRL(Op, DAG, getPointerTy());
+  case ISD::SRA:                return LowerSRA(Op, DAG, getPointerTy());
 
   // Vector-related lowering.
   case ISD::BUILD_VECTOR:       return LowerBUILD_VECTOR(Op, DAG);