[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h

[Evan Cheng]

Changes in directory llvm/include/llvm/Target:

TargetInstrInfo.h updated: 1.87 -> 1.88
---
Log message:

Instructions with variable operands (variable_ops) can have a number required
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.


---
Diffs of the changes:  (+14 -1)

 TargetInstrInfo.h |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletion(-)


Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.87 llvm/include/llvm/Target/TargetInstrInfo.h:1.88
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.87	Thu May 18 15:42:07 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h	Thu Jun 15 02:22:16 2006
@@ -76,6 +76,10 @@
 // block.
 const unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11;
 
+// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra
+// operands in addition to the minimum number operands specified.
+const unsigned M_VARIABLE_OPS = 1 << 12;
+
 // Machine operand flags
 // M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it
 // requires a callback to look up its register class.
@@ -97,7 +101,7 @@
 class TargetInstrDescriptor {
 public:
   const char *    Name;          // Assembly language mnemonic for the opcode.
-  int             numOperands;   // Number of args; -1 if variable #args
+  unsigned        numOperands;   // Num of args (may be more if variable_ops).
   InstrSchedClass schedClass;    // enum  identifying instr sched class
   unsigned        Flags;         // flags identifying machine instr class
   unsigned        TSFlags;       // Target Specific Flag values
@@ -144,6 +148,11 @@
 
   const TargetRegisterClass
   *getInstrOperandRegClass(const TargetInstrDescriptor *II, unsigned Op) const {
+    if (Op >= II->numOperands) {
+      if (II->Flags & M_VARIABLE_OPS)
+        return NULL;
+      assert(false && "Invalid operand # of instruction");
+    }
     const TargetOperandInfo &toi = II->OpInfo[Op];
     return (toi.Flags & M_LOOK_UP_PTR_REG_CLASS)
            ? getPointerRegClass() : toi.RegClass;
@@ -212,6 +221,10 @@
     return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION;
   }
 
+  bool hasVariableOperands(MachineOpCode Opcode) const {
+    return get(Opcode).Flags & M_VARIABLE_OPS;
+  }
+
   /// Return true if the instruction is a register to register move
   /// and leave the source and dest operands in the passed parameters.
   virtual bool isMoveInstr(const MachineInstr& MI,