[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.10 -> 1.11
---
Log message:

add R0 to liveout
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch



---
Diffs of the changes:  (+13 -3)

 ARMISelDAGToDAG.cpp |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.10 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.11
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.10	Tue May 30 12:33:19 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Mon Jun  5 17:26:14 2006
@@ -49,18 +49,28 @@
 
 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   SDOperand Copy;
+  SDOperand Chain = Op.getOperand(0);
   switch(Op.getNumOperands()) {
   default:
     assert(0 && "Do not know how to return this many arguments!");
     abort();
-  case 1:
-    return SDOperand(); // ret void is legal
+  case 1: {
+    SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
+    return DAG.getNode(ISD::BRIND, MVT::Other, Chain, LR);
+  }
   case 3:
-    Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
+    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
+    if (DAG.getMachineFunction().liveout_empty())
+      DAG.getMachineFunction().addLiveOut(ARM::R0);
     break;
   }
+
   SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
 
+  //bug: the copy and branch should be linked with a flag so that the
+  //scheduller can't move an instruction that destroys R0 in between them
+  //return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR, Copy.getValue(1));
+
   return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
 }