[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td
Rafael Espindola
rafael.espindola at gmail.com
Tue May 30 10:33:31 PDT 2006
Changes in directory llvm/lib/Target/ARM:
ARMISelDAGToDAG.cpp updated: 1.9 -> 1.10
ARMInstrInfo.td updated: 1.3 -> 1.4
---
Log message:
Expand ret into "CopyToReg;BRIND"
---
Diffs of the changes: (+4 -18)
ARMISelDAGToDAG.cpp | 12 +++---------
ARMInstrInfo.td | 10 +---------
2 files changed, 4 insertions(+), 18 deletions(-)
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.9 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.10
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.9 Fri May 26 18:10:12 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue May 30 12:33:19 2006
@@ -28,13 +28,6 @@
#include <set>
using namespace llvm;
-namespace ARMISD {
- enum {
- FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
- RET_FLAG
- };
-}
-
namespace {
class ARMTargetLowering : public TargetLowering {
public:
@@ -63,11 +56,12 @@
case 1:
return SDOperand(); // ret void is legal
case 3:
- Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
+ Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
break;
}
+ SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
- return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
+ return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
}
static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.3 llvm/lib/Target/ARM/ARMInstrInfo.td:1.4
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.3 Fri May 26 05:56:17 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td Tue May 30 12:33:19 2006
@@ -30,10 +30,6 @@
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq, [SDNPHasChain]>;
-def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
-def retflag : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
- [SDNPHasChain, SDNPOptInFlag]>;
-
def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
[(callseq_end imm:$amt)]>;
@@ -42,11 +38,7 @@
"!ADJCALLSTACKDOWN $amt",
[(callseq_start imm:$amt)]>;
-//bx supports other registers as operands. So this looks like a
-//hack. Maybe a ret should be expanded to a "branch lr" and bx
-//declared as a regular instruction
-
-def BX: InstARM<(ops), "bx lr", [(retflag)]>;
+def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
def ldr : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
"ldr $dst, [$addr]",
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