[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMISelDAGToDAG.cpp ARMInstrInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.1 -> 1.2
ARMISelDAGToDAG.cpp updated: 1.3 -> 1.4
ARMInstrInfo.cpp updated: 1.1 -> 1.2
---
Log message:

implement minimal versions of
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr



---
Diffs of the changes:  (+80 -9)

 ARMAsmPrinter.cpp   |   47 ++++++++++++++++++++++++++++++++++++++++++++---
 ARMISelDAGToDAG.cpp |   37 ++++++++++++++++++++++++++++++++++++-
 ARMInstrInfo.cpp    |    5 -----
 3 files changed, 80 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.1 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.2
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.1	Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Mon May 22 21:48:20 2006
@@ -85,8 +85,50 @@
 /// method to print assembly for each instruction.
 ///
 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
-  assert(0 && "not implemented");
-  // We didn't modify anything.
+  SetupMachineFunction(MF);
+  O << "\n\n";
+
+  // Print out constants referenced by the function
+  EmitConstantPool(MF.getConstantPool());
+
+  // Print out jump tables referenced by the function
+  EmitJumpTableInfo(MF.getJumpTableInfo());
+
+  // Print out labels for the function.
+  const Function *F = MF.getFunction();
+  switch (F->getLinkage()) {
+  default: assert(0 && "Unknown linkage type!");
+  case Function::InternalLinkage:
+    SwitchToTextSection("\t.text", F);
+    break;
+  case Function::ExternalLinkage:
+    SwitchToTextSection("\t.text", F);
+    O << "\t.globl\t" << CurrentFnName << "\n";
+    break;
+  case Function::WeakLinkage:
+  case Function::LinkOnceLinkage:
+    assert(0 && "Not implemented");
+    break;
+  }
+  EmitAlignment(4, F);
+  O << CurrentFnName << ":\n";
+
+  // Print out code for the function.
+  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
+       I != E; ++I) {
+    // Print a label for the basic block.
+    if (I != MF.begin()) {
+      printBasicBlockLabel(I, true);
+      O << '\n';
+    }
+    for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
+         II != E; ++II) {
+      // Print the assembly for the instruction.
+      O << "\t";
+      printInstruction(II);
+    }
+  }
+
   return false;
 }
 
@@ -109,7 +151,6 @@
 }
 
 bool ARMAsmPrinter::doFinalization(Module &M) {
-  assert(0 && "not implemented");
   AsmPrinter::doFinalization(M);
   return false; // success
 }


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.3 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.4
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.3	Thu May 18 16:45:49 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Mon May 22 21:48:20 2006
@@ -82,7 +82,42 @@
 }
 
 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
-  assert(0 && "Not implemented");
+  MachineFunction &MF = DAG.getMachineFunction();
+  SSARegMap *RegMap = MF.getSSARegMap();
+  std::vector<SDOperand> ArgValues;
+  SDOperand Root = Op.getOperand(0);
+
+  unsigned reg_idx = 0;
+  unsigned num_regs = 4;
+
+  static const unsigned REGS[] = {
+    ARM::R0, ARM::R1, ARM::R2, ARM::R3
+  };
+
+  for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+    SDOperand ArgVal;
+
+    MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
+    assert (ObjectVT == MVT::i32);
+
+    assert(reg_idx < num_regs);
+    unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
+    MF.addLiveIn(REGS[reg_idx], VReg);
+    ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+    ++reg_idx;
+
+    ArgValues.push_back(ArgVal);
+  }
+
+  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
+  assert(!isVarArg);
+
+  ArgValues.push_back(Root);
+
+  // Return the new list of results.
+  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
+                                    Op.Val->value_end());
+  return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
 }
 
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.1 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.2
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.1	Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp	Mon May 22 21:48:20 2006
@@ -27,11 +27,6 @@
 ///
 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
                                  unsigned &SrcReg, unsigned &DstReg) const {
-  // We look for 3 kinds of patterns here:
-  // or with G0 or 0
-  // add with G0 or 0
-  // fmovs or FpMOVD (pseudo double move).
-  assert(0 && "not implemented");
   return false;
 }