[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.2 -> 1.3
ARMInstrInfo.td updated: 1.1 -> 1.2
ARMRegisterInfo.cpp updated: 1.2 -> 1.3
---
Log message:

implement movri
add a stub LowerFORMAL_ARGUMENTS



---
Diffs of the changes:  (+14 -3)

 ARMISelDAGToDAG.cpp |    6 ++++++
 ARMInstrInfo.td     |    9 +++++++--
 ARMRegisterInfo.cpp |    2 +-
 3 files changed, 14 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.2 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.3
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.2	Mon May 15 17:34:39 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Thu May 18 16:45:49 2006
@@ -81,11 +81,17 @@
   return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
 }
 
+static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
+  assert(0 && "Not implemented");
+}
+
 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   switch (Op.getOpcode()) {
   default:
     assert(0 && "Should not custom lower this!");
     abort();
+  case ISD::FORMAL_ARGUMENTS:
+    return LowerFORMAL_ARGUMENTS(Op, DAG);
   case ISD::RET:
     return LowerRET(Op, DAG);
   }


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.1 llvm/lib/Target/ARM/ARMInstrInfo.td:1.2
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.1	Sun May 14 17:18:28 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Thu May 18 16:45:49 2006
@@ -42,6 +42,8 @@
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;
 
+def BX: InstARM<(ops), "bx", [(retflag)]>;
+
 def ldr   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
                      "ldr $dst, [$addr]",
                      [(set IntRegs:$dst, (load IntRegs:$addr))]>;
@@ -50,5 +52,8 @@
                     "str $src, [$addr]",
                     [(store IntRegs:$src, IntRegs:$addr)]>;
 
-def mov   : InstARM<(ops IntRegs:$dst, IntRegs:$b),
-                    "mov $dst, $b", []>;
+def movrr   : InstARM<(ops IntRegs:$dst, IntRegs:$src),
+                       "mov $dst, $src", []>;
+
+def movri   : InstARM<(ops IntRegs:$dst, i32imm:$src),
+                       "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.2 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.3
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.2	Wed May 17 19:11:26 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Thu May 18 16:45:49 2006
@@ -49,7 +49,7 @@
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *RC) const {
   assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::mov, 1, DestReg).addReg(SrcReg);
+  BuildMI(MBB, I, ARM::movrr, 1, DestReg).addReg(SrcReg);
 }
 
 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,