[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp CodeGenTarget.h DAGISelEmitter.cpp

[Evan Cheng]

Changes in directory llvm/utils/TableGen:

CodeGenTarget.cpp updated: 1.63 -> 1.64
CodeGenTarget.h updated: 1.25 -> 1.26
DAGISelEmitter.cpp updated: 1.202 -> 1.203
---
Log message:

Allow patterns to refer to physical registers that belong to multiple
register classes.


---
Diffs of the changes:  (+26 -6)

 CodeGenTarget.cpp  |   17 +++++++++++++++++
 CodeGenTarget.h    |    4 ++++
 DAGISelEmitter.cpp |   11 +++++------
 3 files changed, 26 insertions(+), 6 deletions(-)


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.63 llvm/utils/TableGen/CodeGenTarget.cpp:1.64
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.63	Mon Apr 10 17:02:59 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Tue May 16 02:05:30 2006
@@ -163,6 +163,23 @@
   RegisterClasses.assign(RegClasses.begin(), RegClasses.end());
 }
 
+std::vector<unsigned char> CodeGenTarget::getRegisterVTs(Record *R) const {
+  std::vector<unsigned char> Result;
+  const std::vector<CodeGenRegisterClass> &RCs = getRegisterClasses();
+  for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+    const CodeGenRegisterClass &RC = RegisterClasses[i];
+    for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) {
+      if (R == RC.Elements[ei]) {
+        const std::vector<MVT::ValueType> &InVTs = RC.getValueTypes();
+        for (unsigned i = 0, e = InVTs.size(); i != e; ++i)
+          Result.push_back(InVTs[i]);
+      }
+    }
+  }
+  return Result;
+}
+
+
 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
   // Rename anonymous register classes.
   if (R->getName().size() > 9 && R->getName()[9] == '.') {


Index: llvm/utils/TableGen/CodeGenTarget.h
diff -u llvm/utils/TableGen/CodeGenTarget.h:1.25 llvm/utils/TableGen/CodeGenTarget.h:1.26
--- llvm/utils/TableGen/CodeGenTarget.h:1.25	Mon Mar 27 16:48:18 2006
+++ llvm/utils/TableGen/CodeGenTarget.h	Tue May 16 02:05:30 2006
@@ -110,6 +110,10 @@
     }
     return FoundRC;
   }
+
+  /// getRegisterVTs - Find the union of all possible ValueTypes for the
+  /// specified physical register.
+  std::vector<unsigned char> getRegisterVTs(Record *R) const;
   
   const std::vector<MVT::ValueType> &getLegalValueTypes() const {
     if (LegalValueTypes.empty()) ReadLegalValueTypes();


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.202 llvm/utils/TableGen/DAGISelEmitter.cpp:1.203
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.202	Fri May 12 02:42:01 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Tue May 16 02:05:30 2006
@@ -565,12 +565,8 @@
   } else if (R->isSubClassOf("Register")) {
     if (NotRegisters) 
       return Unknown;
-    // If the register appears in exactly one regclass, and the regclass has one
-    // value type, use it as the known type.
     const CodeGenTarget &T = TP.getDAGISelEmitter().getTargetInfo();
-    if (const CodeGenRegisterClass *RC = T.getRegisterClassForRegister(R))
-      return ConvertVTs(RC->getValueTypes());
-    return Unknown;
+    return T.getRegisterVTs(R);
   } else if (R->isSubClassOf("ValueType") || R->isSubClassOf("CondCode")) {
     // Using a VTSDNode or CondCodeSDNode.
     return Other;
@@ -607,7 +603,10 @@
         // At some point, it may make sense for this tree pattern to have
         // multiple types.  Assert here that it does not, so we revisit this
         // code when appropriate.
-        assert(getExtTypes().size() == 1 && "TreePattern has too many types!");
+        assert(getExtTypes().size() >= 1 && "TreePattern does not have a type!");
+        MVT::ValueType VT = getTypeNum(0);
+        for (unsigned i = 1, e = getExtTypes().size(); i != e; ++i)
+          assert(getTypeNum(i) == VT && "TreePattern has too many types!");
         
         unsigned Size = MVT::getSizeInBits(getTypeNum(0));
         // Make sure that the value is representable for this type.