[llvm-commits] CVS: llvm/include/llvm/CodeGen/ScheduleDAG.h

[Evan Cheng]

Changes in directory llvm/include/llvm/CodeGen:

ScheduleDAG.h updated: 1.24 -> 1.25
---
Log message:

Add capability to scheduler to commute nodes for profit. 
If a two-address code whose first operand has uses below, it should be commuted
when possible.


---
Diffs of the changes:  (+5 -4)

 ScheduleDAG.h |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)


Index: llvm/include/llvm/CodeGen/ScheduleDAG.h
diff -u llvm/include/llvm/CodeGen/ScheduleDAG.h:1.24 llvm/include/llvm/CodeGen/ScheduleDAG.h:1.25
--- llvm/include/llvm/CodeGen/ScheduleDAG.h:1.24	Thu May 11 18:55:42 2006
+++ llvm/include/llvm/CodeGen/ScheduleDAG.h	Thu May 11 20:58:24 2006
@@ -91,7 +91,7 @@
     short NumChainPredsLeft;            // # of chain preds not scheduled.
     short NumChainSuccsLeft;            // # of chain succs not scheduled.
     bool isTwoAddress     : 1;          // Is a two-address instruction.
-    bool isDefNUseOperand : 1;          // Is a def&use operand.
+    bool isCommutable     : 1;          // Is a commutable instruction.
     bool isPending        : 1;          // True once pending.
     bool isAvailable      : 1;          // True once available.
     bool isScheduled      : 1;          // True once scheduled.
@@ -105,7 +105,7 @@
     SUnit(SDNode *node, unsigned nodenum)
       : Node(node), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0),
         NumChainPredsLeft(0), NumChainSuccsLeft(0),
-        isTwoAddress(false), isDefNUseOperand(false),
+        isTwoAddress(false), isCommutable(false),
         isPending(false), isAvailable(false), isScheduled(false),
         Latency(0), CycleBound(0), Cycle(0), Depth(0), Height(0),
         NodeNum(nodenum) {}
@@ -162,10 +162,11 @@
     const MRegisterInfo *MRI;             // Target processor register info
     SSARegMap *RegMap;                    // Virtual/real register map
     MachineConstantPool *ConstPool;       // Target constant pool
-    std::vector<SUnit*> Sequence;         // The schedule.  Null SUnit*'s represent
-                                          // noop instructions.
+    std::vector<SUnit*> Sequence;         // The schedule. Null SUnit*'s
+                                          // represent noop instructions.
     std::map<SDNode*, SUnit*> SUnitMap;   // SDNode to SUnit mapping (n -> 1).
     std::vector<SUnit> SUnits;            // The scheduling units.
+    std::set<SDNode*> CommuteSet;         // Nodes the should be commuted.
 
     ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
                 const TargetMachine &tm)