[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.cpp updated: 1.19 -> 1.20
PPCRegisterInfo.cpp updated: 1.64 -> 1.65
---
Log message:

Move some methods out of MachineInstr into MachineOperand


---
Diffs of the changes:  (+6 -6)

 PPCInstrInfo.cpp    |    4 ++--
 PPCRegisterInfo.cpp |    8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.20
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19	Thu Mar 16 16:24:02 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp	Thu May  4 12:52:23 2006
@@ -136,8 +136,8 @@
   // Swap op1/op2
   unsigned Reg1 = MI->getOperand(1).getReg();
   unsigned Reg2 = MI->getOperand(2).getReg();
-  MI->SetMachineOperandReg(2, Reg1);
-  MI->SetMachineOperandReg(1, Reg2);
+  MI->getOperand(2).setReg(Reg1);
+  MI->getOperand(1).setReg(Reg2);
   
   // Swap the mask around.
   unsigned MB = MI->getOperand(4).getImmedValue();


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.64 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.65
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.64	Thu May  4 12:21:19 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp	Thu May  4 12:52:23 2006
@@ -294,7 +294,7 @@
   int FrameIndex = MI.getOperand(i).getFrameIndex();
 
   // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
-  MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
+  MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
 
   // Take into account whether it's an add or mem instruction
   unsigned OffIdx = (i == 2) ? 1 : 2;
@@ -321,8 +321,8 @@
            "No indexed form of load or store available!");
     unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
     MI.setOpcode(NewOpcode);
-    MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
-    MI.SetMachineOperandReg(2, PPC::R0);
+    MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
+    MI.getOperand(2).ChangeToRegister(PPC::R0);
   } else {
     switch (MI.getOpcode()) {
     case PPC::LWA:
@@ -333,7 +333,7 @@
       Offset >>= 2;    // The actual encoded value has the low two bits zero.
       break;
     }
-    MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
+    MI.getOperand(OffIdx).ChangeToImmediate(Offset);
   }
 }