[llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp IA64InstrBuilder.h IA64RegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/IA64:

IA64AsmPrinter.cpp updated: 1.30 -> 1.31
IA64InstrBuilder.h updated: 1.2 -> 1.3
IA64RegisterInfo.cpp updated: 1.17 -> 1.18
---
Log message:

There shalt be only one "immediate" operand type!



---
Diffs of the changes:  (+11 -12)

 IA64AsmPrinter.cpp   |    7 +++----
 IA64InstrBuilder.h   |    6 +++---
 IA64RegisterInfo.cpp |   10 +++++-----
 3 files changed, 11 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.30 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.31
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.30	Wed May  3 20:15:02 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp	Thu May  4 12:21:19 2006
@@ -170,16 +170,15 @@
 }
 
 void IA64AsmPrinter::printOp(const MachineOperand &MO,
-                                 bool isBRCALLinsn /* = false */) {
+                             bool isBRCALLinsn /* = false */) {
   const MRegisterInfo &RI = *TM.getRegisterInfo();
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
     O << RI.get(MO.getReg()).Name;
     return;
 
-  case MachineOperand::MO_SignExtendedImmed:
-  case MachineOperand::MO_UnextendedImmed:
-    O << /*(unsigned int)*/MO.getImmedValue();
+  case MachineOperand::MO_Immediate:
+    O << MO.getImmedValue();
     return;
   case MachineOperand::MO_MachineBasicBlock:
     printBasicBlockLabel(MO.getMachineBasicBlock());


Index: llvm/lib/Target/IA64/IA64InstrBuilder.h
diff -u llvm/lib/Target/IA64/IA64InstrBuilder.h:1.2 llvm/lib/Target/IA64/IA64InstrBuilder.h:1.3
--- llvm/lib/Target/IA64/IA64InstrBuilder.h:1.2	Thu Apr 21 18:13:11 2005
+++ llvm/lib/Target/IA64/IA64InstrBuilder.h	Thu May  4 12:21:19 2006
@@ -29,9 +29,9 @@
 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
                   bool mem = true) {
   if (mem)
-    return MIB.addSImm(Offset).addFrameIndex(FI);
+    return MIB.addImm(Offset).addFrameIndex(FI);
   else
-    return MIB.addFrameIndex(FI).addSImm(Offset);
+    return MIB.addFrameIndex(FI).addImm(Offset);
 }
 
 /// addConstantPoolReference - This function is used to add a reference to the
@@ -43,7 +43,7 @@
 inline const MachineInstrBuilder&
 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
                          int Offset = 0) {
-  return MIB.addSImm(Offset).addConstantPoolIndex(CPI);
+  return MIB.addImm(Offset).addConstantPoolIndex(CPI);
 }
 
 } // End llvm namespace


Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.17 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.18
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.17	Fri Apr  7 11:34:45 2006
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp	Thu May  4 12:21:19 2006
@@ -122,11 +122,11 @@
       MachineInstr *New;
       if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
         New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
-          .addSImm(-Amount);
+          .addImm(-Amount);
       } else {
         assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
         New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
-          .addSImm(Amount);
+          .addImm(Amount);
       }
 
       // Replace the pseudo instruction with a new instruction...
@@ -173,7 +173,7 @@
                                // (the bundler wants to know this)
     //insert the new
     MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
-      .addReg(BaseRegister).addSImm(Offset);
+      .addReg(BaseRegister).addImm(Offset);
     MBB.insert(II, nMI);
   } else { // it's big
     //fix up the old:
@@ -181,7 +181,7 @@
     MI.getOperand(i).setUse(); // mark r22 as being used
                                // (the bundler wants to know this)
     MachineInstr* nMI;
-    nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
+    nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
     MBB.insert(II, nMI);
     nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
       .addReg(IA64::r22);
@@ -272,7 +272,7 @@
     MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
     MBB.insert(MBBI, MI);
   } else { // we use r22 as a scratch register here
-    MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes);
+    MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
     // FIXME: MOVLSI32 expects a _u_32imm
     MBB.insert(MBBI, MI);  // first load the decrement into r22
     MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);