[llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp

Chris Lattner lattner at cs.uiuc.edu
Wed May 3 17:50:13 PDT 2006



Changes in directory llvm/lib/CodeGen:

MachineInstr.cpp updated: 1.112 -> 1.113
---
Log message:

Remove some more V9-specific stuff.


---
Diffs of the changes:  (+2 -32)

 MachineInstr.cpp |   34 ++--------------------------------
 1 files changed, 2 insertions(+), 32 deletions(-)


Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.112 llvm/lib/CodeGen/MachineInstr.cpp:1.113
--- llvm/lib/CodeGen/MachineInstr.cpp:1.112	Wed May  3 19:44:25 2006
+++ llvm/lib/CodeGen/MachineInstr.cpp	Wed May  3 19:49:59 2006
@@ -176,18 +176,6 @@
 
   if (TM) MRI = TM->getRegisterInfo();
 
-  bool CloseParen = true;
-  if (MO.isHiBits32())
-    OS << "%lm(";
-  else if (MO.isLoBits32())
-    OS << "%lo(";
-  else if (MO.isHiBits64())
-    OS << "%hh(";
-  else if (MO.isLoBits64())
-    OS << "%hm(";
-  else
-    CloseParen = false;
-
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
     if (MO.getVRegValue()) {
@@ -235,9 +223,6 @@
   default:
     assert(0 && "Unrecognized operand type");
   }
-
-  if (CloseParen)
-    OS << ")";
 }
 
 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
@@ -272,8 +257,7 @@
   OS << "\n";
 }
 
-namespace llvm {
-std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
+std::ostream &llvm::operator<<(std::ostream &os, const MachineInstr &MI) {
   // If the instruction is embedded into a basic block, we can find the target
   // info for the instruction.
   if (const MachineBasicBlock *MBB = MI.getParent()) {
@@ -301,16 +285,7 @@
   return os << "\n";
 }
 
-std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
-  if (MO.isHiBits32())
-    OS << "%lm(";
-  else if (MO.isLoBits32())
-    OS << "%lo(";
-  else if (MO.isHiBits64())
-    OS << "%hh(";
-  else if (MO.isLoBits64())
-    OS << "%hm(";
-
+std::ostream &llvm::operator<<(std::ostream &OS, const MachineOperand &MO) {
   switch (MO.getType()) {
   case MachineOperand::MO_VirtualRegister:
     if (MO.hasAllocatedReg())
@@ -356,10 +331,5 @@
     break;
   }
 
-  if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
-    OS << ")";
-
   return OS;
 }
-
-}






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