[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.150 -> 1.151
---
Log message:

Remove a bogus transformation.  This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
with some changes I have to the new CFE.


---
Diffs of the changes:  (+0 -7)

 DAGCombiner.cpp |    7 -------
 1 files changed, 7 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.150 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.151
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.150	Fri Apr 21 10:32:26 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Apr 28 18:33:20 2006
@@ -1899,13 +1899,6 @@
   // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
   if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
     return DAG.getZeroExtendInReg(N0, EVT);
-  // fold (sext_in_reg (srl x)) -> sra x
-  if (N0.getOpcode() == ISD::SRL && 
-      N0.getOperand(1).getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
-    return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 
-                       N0.getOperand(1));
-  }
   // fold (sext_inreg (extload x)) -> (sextload x)
   if (N0.getOpcode() == ISD::EXTLOAD && 
       EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&