[llvm-commits] CVS: llvm/lib/Target/IA64/IA64AsmPrinter.cpp IA64ISelLowering.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/IA64:

IA64AsmPrinter.cpp updated: 1.25 -> 1.26
IA64ISelLowering.cpp updated: 1.36 -> 1.37
---
Log message:

JumpTable support!  What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.


---
Diffs of the changes:  (+3 -7)

 IA64AsmPrinter.cpp   |    9 ++-------
 IA64ISelLowering.cpp |    1 +
 2 files changed, 3 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.25 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.26
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.25	Mon Mar 13 17:20:37 2006
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp	Sat Apr 22 13:53:45 2006
@@ -189,14 +189,9 @@
   case MachineOperand::MO_UnextendedImmed:
     O << /*(unsigned int)*/MO.getImmedValue();
     return;
-  case MachineOperand::MO_MachineBasicBlock: {
-    MachineBasicBlock *MBBOp = MO.getMachineBasicBlock();
-    O << PrivateGlobalPrefix << "LBB"
-      << Mang->getValueName(MBBOp->getParent()->getFunction())
-      << "_" << MBBOp->getNumber () << "\t// "
-      << MBBOp->getBasicBlock ()->getName ();
+  case MachineOperand::MO_MachineBasicBlock:
+    printBasicBlockLabel(MO.getMachineBasicBlock());
     return;
-  }
   case MachineOperand::MO_PCRelativeDisp:
     std::cerr << "Shouldn't use addPCDisp() when building IA64 MachineInstrs";
     abort ();


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.36 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.37
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.36	Thu Mar 16 19:40:33 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Sat Apr 22 13:53:45 2006
@@ -35,6 +35,7 @@
       // register class for predicate registers
       addRegisterClass(MVT::i1, IA64::PRRegisterClass);
 
+      setOperationAction(ISD::BRIND            , MVT::i64,   Expand);
       setOperationAction(ISD::BR_CC            , MVT::Other, Expand);
       setOperationAction(ISD::FP_ROUND_INREG   , MVT::f32  , Expand);