[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.176 -> 1.177
---
Log message:

Handle v2i64 BUILD_VECTOR custom lowering correctly. v2i64 is a legal type,
but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.


---
Diffs of the changes:  (+16 -1)

 X86ISelLowering.cpp |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.176 llvm/lib/Target/X86/X86ISelLowering.cpp:1.177
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.176	Wed Apr 19 18:28:59 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Apr 19 19:11:39 2006
@@ -2980,7 +2980,22 @@
       if (Elt0IsZero) return Op;
 
       // Zero extend a scalar to a vector.
-      return DAG.getNode(X86ISD::ZEXT_S2VEC, Op.getValueType(), Elt0);
+      if (Elt0.getValueType() != MVT::i64)
+        return DAG.getNode(X86ISD::ZEXT_S2VEC, Op.getValueType(), Elt0);
+
+      // See if we can turn it into a f64 op.
+      bool IsLegal = false;
+      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt0)) {
+        Elt0 = DAG.getConstantFP(BitsToDouble(C->getValue()), MVT::f64);
+        IsLegal = true;
+      } else if (Elt0.getOpcode() == ISD::LOAD) {
+        Elt0 = DAG.getLoad(MVT::f64, Elt0.getOperand(0), Elt0.getOperand(1),
+                           Elt0.getOperand(2));
+        IsLegal = true;
+      }
+      if (IsLegal)
+        return DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
+                           DAG.getNode(X86ISD::ZEXT_S2VEC, MVT::v2f64, Elt0));
     }
 
     if (Values.size() > 2) {