[llvm-commits] CVS: llvm/lib/Target/Target.td TargetSelectionDAG.td

[Evan Cheng]

Changes in directory llvm/lib/Target:

Target.td updated: 1.75 -> 1.76
TargetSelectionDAG.td updated: 1.64 -> 1.65
---
Log message:

Allow "let AddedCost = n in" to increase pattern complexity.


---
Diffs of the changes:  (+5 -1)

 Target.td             |    3 +++
 TargetSelectionDAG.td |    3 ++-
 2 files changed, 5 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.75 llvm/lib/Target/Target.td:1.76
--- llvm/lib/Target/Target.td:1.75	Fri Mar 24 15:13:21 2006
+++ llvm/lib/Target/Target.td	Wed Apr 19 13:07:24 2006
@@ -144,6 +144,9 @@
   // code.
   list<Predicate> Predicates = [];
 
+  // Added cost passed onto matching pattern.
+  int AddedCost  = 0;
+
   // These bits capture information about the high-level semantics of the
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?


Index: llvm/lib/Target/TargetSelectionDAG.td
diff -u llvm/lib/Target/TargetSelectionDAG.td:1.64 llvm/lib/Target/TargetSelectionDAG.td:1.65
--- llvm/lib/Target/TargetSelectionDAG.td:1.64	Sat Apr 15 18:39:14 2006
+++ llvm/lib/Target/TargetSelectionDAG.td	Wed Apr 19 13:07:24 2006
@@ -313,7 +313,7 @@
 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
     SDTypeProfile<1, 2, []>, []>;
 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
-    SDTypeProfile<1, 3, []>, []>;
+    SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>]>, []>;
 
 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
 // these internally.  Don't reference these directly.
@@ -473,6 +473,7 @@
   dag             PatternToMatch = patternToMatch;
   list<dag>       ResultInstrs   = resultInstrs;
   list<Predicate> Predicates     = [];  // See class Instruction in Target.td.
+  int             AddedCost      = 0;   // See class Instruction in Target.td.
 }
 
 // Pat - A simple (but common) form of a pattern, which produces a simple result