[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.172 -> 1.173
X86InstrSSE.td updated: 1.99 -> 1.100
---
Log message:

Use movss to insert_vector_elt(v, s, 0).


---
Diffs of the changes:  (+37 -19)

 X86ISelLowering.cpp |   51 ++++++++++++++++++++++++++++++++-------------------
 X86InstrSSE.td      |    5 +++++
 2 files changed, 37 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.172 llvm/lib/Target/X86/X86ISelLowering.cpp:1.173
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.172	Mon Apr 17 17:04:06 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Mon Apr 17 17:45:49 2006
@@ -3015,28 +3015,41 @@
         N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
       return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
     } else if (MVT::getSizeInBits(BaseVT) == 32) {
-      // Use two pinsrw instructions to insert a 32 bit value.
       unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
-      Idx <<= 1;
-      if (MVT::isFloatingPoint(N1.getValueType())) {
-        if (N1.getOpcode() == ISD::LOAD) {
-          // Just load directly from f32mem to R32.
-          N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
-                           N1.getOperand(2));
-        } else {
-          N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
-          N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
-          N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
-                           DAG.getConstant(0, MVT::i32));
+      if (Idx == 0) {
+        // Use a movss.
+        N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
+        MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
+        MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
+        std::vector<SDOperand> MaskVec;
+        MaskVec.push_back(DAG.getConstant(4, BaseVT));
+        for (unsigned i = 1; i <= 3; ++i)
+          MaskVec.push_back(DAG.getConstant(i, BaseVT));
+        return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
+                           DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec));
+      } else {
+        // Use two pinsrw instructions to insert a 32 bit value.
+        Idx <<= 1;
+        if (MVT::isFloatingPoint(N1.getValueType())) {
+          if (N1.getOpcode() == ISD::LOAD) {
+            // Just load directly from f32mem to R32.
+            N1 = DAG.getLoad(MVT::i32, N1.getOperand(0), N1.getOperand(1),
+                             N1.getOperand(2));
+          } else {
+            N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
+            N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
+            N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
+                             DAG.getConstant(0, MVT::i32));
+          }
         }
+        N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
+        N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
+                         DAG.getConstant(Idx, MVT::i32));
+        N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
+        N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
+                         DAG.getConstant(Idx+1, MVT::i32));
+        return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
       }
-      N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
-      N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
-                       DAG.getConstant(Idx, MVT::i32));
-      N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
-      N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
-                       DAG.getConstant(Idx+1, MVT::i32));
-      return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
     }
 
     return SDOperand();


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.99 llvm/lib/Target/X86/X86InstrSSE.td:1.100
--- llvm/lib/Target/X86/X86InstrSSE.td:1.99	Mon Apr 17 16:33:57 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Mon Apr 17 17:45:49 2006
@@ -2414,6 +2414,11 @@
                   MOVSLDUP_shuffle_mask)),
           (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
 
+// vector_shuffle v1, v2 <4, 1, 2, 3>
+def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
+                  MOVS_shuffle_mask)),
+          (MOVLPSrr VR128:$src1, VR128:$src2)>;
+
 // 128-bit logical shifts
 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
           (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,