[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.145 -> 1.146
SelectionDAGISel.cpp updated: 1.219 -> 1.220
---
Log message:

Codegen shufflevector as VVECTOR_SHUFFLE


---
Diffs of the changes:  (+25 -2)

 DAGCombiner.cpp      |   13 ++++++++++++-
 SelectionDAGISel.cpp |   14 +++++++++++++-
 2 files changed, 25 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.145 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.146
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.145	Thu Apr  6 18:20:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Apr  7 23:15:24 2006
@@ -1447,6 +1447,12 @@
     AddToWorkList(XORNode.Val);
     return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
   }
+
+  // Simplify the expression using non-local knowledge.
+  if (!MVT::isVector(VT) &&
+      SimplifyDemandedBits(SDOperand(N, 0)))
+    return SDOperand();
+  
   return SDOperand();
 }
 
@@ -2044,8 +2050,10 @@
   // type, convert each element.  This handles FP<->INT cases.
   if (SrcBitSize == DstBitSize) {
     std::vector<SDOperand> Ops;
-    for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i)
+    for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
       Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
+      AddToWorkList(Ops.back().Val);
+    }
     Ops.push_back(*(BV->op_end()-2)); // Add num elements.
     Ops.push_back(DAG.getValueType(DstEltVT));
     return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
@@ -2635,6 +2643,7 @@
       UnOps.push_back(NumElts);
       UnOps.push_back(EltType);
       Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
+      AddToWorkList(Ops.back().Val);
     }
     Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
     Ops.push_back(NumElts);
@@ -2690,6 +2699,7 @@
     }
     ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
                            MappedOps);
+    AddToWorkList(ShufMask.Val);
     return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
                        N->getOperand(0), 
                        DAG.getNode(ISD::UNDEF, N->getValueType(0)),
@@ -2755,6 +2765,7 @@
            RHSOp.getOpcode() != ISD::ConstantFP))
         break;
       Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
+      AddToWorkList(Ops.back().Val);
       assert((Ops.back().getOpcode() == ISD::UNDEF ||
               Ops.back().getOpcode() == ISD::Constant ||
               Ops.back().getOpcode() == ISD::ConstantFP) &&


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.219 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.220
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.219	Fri Apr  7 20:19:25 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Fri Apr  7 23:15:24 2006
@@ -516,7 +516,7 @@
 
   void visitExtractElement(User &I);
   void visitInsertElement(User &I);
-  void visitShuffleVector(User &I) { assert(0 && "ShuffleVector not impl!"); }
+  void visitShuffleVector(User &I);
 
   void visitGetElementPtr(User &I);
   void visitCast(User &I);
@@ -1076,6 +1076,18 @@
                            TLI.getValueType(I.getType()), InVec, InIdx));
 }
 
+void SelectionDAGLowering::visitShuffleVector(User &I) {
+  SDOperand V1   = getValue(I.getOperand(0));
+  SDOperand V2   = getValue(I.getOperand(1));
+  SDOperand Mask = getValue(I.getOperand(2));
+
+  SDOperand Num = *(V1.Val->op_end()-2);
+  SDOperand Typ = *(V2.Val->op_end()-1);
+  setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
+                           V1, V2, Mask, Num, Typ));
+}
+
+
 void SelectionDAGLowering::visitGetElementPtr(User &I) {
   SDOperand N = getValue(I.getOperand(0));
   const Type *Ty = I.getOperand(0)->getType();