[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.131 -> 1.132
---
Log message:

Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')


---
Diffs of the changes:  (+30 -0)

 DAGCombiner.cpp |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.132
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.131	Tue Mar 28 14:28:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Mar 28 16:11:53 2006
@@ -212,6 +212,7 @@
     SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
     SDOperand visitVBUILD_VECTOR(SDNode *N);
+    SDOperand visitVECTOR_SHUFFLE(SDNode *N);
 
     SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
     
@@ -646,6 +647,7 @@
   case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
   case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
   case ISD::VBUILD_VECTOR:      return visitVBUILD_VECTOR(N);
+  case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
   }
   return SDOperand();
 }
@@ -2427,6 +2429,34 @@
   return SDOperand();
 }
 
+SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
+  // If the LHS and the RHS are the same node, turn the RHS into an undef.
+  if (N->getOperand(0) == N->getOperand(1)) {
+    // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
+    // first operand.
+    std::vector<SDOperand> MappedOps;
+    SDOperand ShufMask = N->getOperand(2);
+    unsigned NumElts = ShufMask.getNumOperands();
+    for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
+      if (cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() >= NumElts) {
+        unsigned NewIdx = 
+           cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
+        MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+      } else {
+        MappedOps.push_back(ShufMask.getOperand(i));
+      }
+    }
+    ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
+                           MappedOps);
+    return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
+                       N->getOperand(0), 
+                       DAG.getNode(ISD::UNDEF, N->getValueType(0)),
+                       ShufMask);
+  }
+ 
+  return SDOperand();
+}
+
 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
   assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");