[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86TargetMachine.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.133 -> 1.134
X86TargetMachine.cpp updated: 1.110 -> 1.111
---
Log message:

SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now 
properly updated in the x86, ppc, and sparc select lowering code.


---
Diffs of the changes:  (+16 -5)

 X86ISelLowering.cpp  |   10 +++++++++-
 X86TargetMachine.cpp |   11 +++++++----
 2 files changed, 16 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.133 llvm/lib/Target/X86/X86ISelLowering.cpp:1.134
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.133	Sun Mar 26 03:53:12 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Sun Mar 26 19:32:24 2006
@@ -1275,7 +1275,15 @@
     MachineFunction *F = BB->getParent();
     F->getBasicBlockList().insert(It, copy0MBB);
     F->getBasicBlockList().insert(It, sinkMBB);
-    // Update machine-CFG edges
+    // Update machine-CFG edges by first adding all successors of the current
+    // block to the new block which will contain the Phi node for the select.
+    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 
+        e = BB->succ_end(); i != e; ++i)
+      sinkMBB->addSuccessor(*i);
+    // Next, remove all successors of the current block, and add the true
+    // and fallthrough blocks as its successors.
+    while(!BB->succ_empty())
+      BB->removeSuccessor(BB->succ_begin());
     BB->addSuccessor(copy0MBB);
     BB->addSuccessor(sinkMBB);
   


Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.110 llvm/lib/Target/X86/X86TargetMachine.cpp:1.111
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.110	Wed Mar 22 23:43:16 2006
+++ llvm/lib/Target/X86/X86TargetMachine.cpp	Sun Mar 26 19:32:24 2006
@@ -36,7 +36,8 @@
   cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
                               cl::desc("Disable the X86 asm printer, for use "
                                        "when profiling the code generator."));
-
+  cl::opt<bool> DisableLowerSwitch("disable-lower-switch", cl::Hidden,
+                                   cl::desc("Disable the LowerSwitch pass"));
   // Register the target.
   RegisterTarget<X86TargetMachine> X("x86", "  IA-32 (Pentium and above)");
 }
@@ -100,8 +101,9 @@
   PM.add(createLowerInvokePass());
 
   // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
+  if (!DisableLowerSwitch)
+    PM.add(createLowerSwitchPass());
+  
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
@@ -168,7 +170,8 @@
   PM.add(createLowerInvokePass());
 
   // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
+  if (!DisableLowerSwitch)
+    PM.add(createLowerSwitchPass());
 
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());