[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td
Evan Cheng
evan.cheng at apple.com
Fri Mar 24 17:33:50 PST 2006
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.130 -> 1.131
X86InstrSSE.td updated: 1.28 -> 1.29
---
Log message:
Added 128-bit packed integer subtraction.
---
Diffs of the changes: (+26 -0)
X86ISelLowering.cpp | 3 +++
X86InstrSSE.td | 23 +++++++++++++++++++++++
2 files changed, 26 insertions(+)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.130 llvm/lib/Target/X86/X86ISelLowering.cpp:1.131
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.130 Fri Mar 24 17:15:12 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Mar 24 19:33:37 2006
@@ -294,6 +294,9 @@
setOperationAction(ISD::ADD, MVT::v8i16, Legal);
setOperationAction(ISD::ADD, MVT::v4i32, Legal);
setOperationAction(ISD::SUB, MVT::v2f64, Legal);
+ setOperationAction(ISD::SUB, MVT::v16i8, Legal);
+ setOperationAction(ISD::SUB, MVT::v8i16, Legal);
+ setOperationAction(ISD::SUB, MVT::v4i32, Legal);
setOperationAction(ISD::MUL, MVT::v2f64, Legal);
setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
setOperationAction(ISD::LOAD, MVT::v16i8, Legal);
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.28 llvm/lib/Target/X86/X86InstrSSE.td:1.29
--- llvm/lib/Target/X86/X86InstrSSE.td:1.28 Fri Mar 24 19:00:18 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Mar 24 19:33:37 2006
@@ -862,6 +862,29 @@
"paddd {$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (v4i32 (add VR128:$src1,
(load addr:$src2))))]>;
+
+def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ "psubb {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
+def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ "psubw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
+def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
+ "psubd {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
+
+def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ "psubb {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (v16i8 (sub VR128:$src1,
+ (load addr:$src2))))]>;
+def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ "psubw {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (v8i16 (sub VR128:$src1,
+ (load addr:$src2))))]>;
+def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
+ "psubd {$src2, $dst|$dst, $src2}",
+ [(set VR128:$dst, (v4i32 (sub VR128:$src1,
+ (load addr:$src2))))]>;
}
//===----------------------------------------------------------------------===//
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