[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.335 -> 1.336
---
Log message:

legalize vbit_convert nodes whose result is a legal type.
Legalize intrinsic nodes.



---
Diffs of the changes:  (+38 -0)

 LegalizeDAG.cpp |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.335 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.336
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.335	Thu Mar 23 19:17:21 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Mar 23 20:26:29 2006
@@ -552,6 +552,14 @@
     }
     break;
   }
+    
+  case ISD::INTRINSIC: {
+    std::vector<SDOperand> Ops;
+    for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
+      Ops.push_back(LegalizeOp(Node->getOperand(i)));
+    Result = DAG.UpdateNodeOperands(Result, Ops);
+    break;
+  }    
 
   case ISD::LOCATION:
     assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
@@ -2312,6 +2320,36 @@
       }
     }
     break;
+  case ISD::VBIT_CONVERT: {
+    assert(Op.getOperand(0).getValueType() == MVT::Vector &&
+           "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
+    
+    // The input has to be a vector type, we have to either scalarize it, pack
+    // it, or convert it based on whether the input vector type is legal.
+    SDNode *InVal = Node->getOperand(0).Val;
+    unsigned NumElems =
+      cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
+    MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
+    
+    // Figure out if there is a Packed type corresponding to this Vector
+    // type.  If so, convert to the packed type.
+    MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
+    if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
+      // Turn this into a bit convert of the packed input.
+      Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 
+                           PackVectorOp(Node->getOperand(0), TVT));
+      break;
+    } else if (NumElems == 1) {
+      // Turn this into a bit convert of the scalar input.
+      Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 
+                           PackVectorOp(Node->getOperand(0), EVT));
+      break;
+    } else {
+      // FIXME: UNIMP!  Store then reload
+      assert(0 && "Cast from unsupported vector type not implemented yet!");
+    }
+  }
+      
     // Conversion operators.  The source and destination have different types.
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP: {