[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.121 -> 1.122
X86ISelLowering.h updated: 1.37 -> 1.38
---
Log message:

Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
64-bit vector shuffle.


---
Diffs of the changes:  (+5 -2)

 X86ISelLowering.cpp |    5 ++++-
 X86ISelLowering.h   |    2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.121 llvm/lib/Target/X86/X86ISelLowering.cpp:1.122
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.121	Wed Mar 22 13:22:18 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Mar 22 16:07:06 2006
@@ -2371,7 +2371,10 @@
 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
 /// are assumed to be legal.
-bool X86TargetLowering::isShuffleMaskLegal(SDOperand Mask) const {
+bool
+X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
+  // Only do shuffles on 128-bit vector types for now.
+  if (MVT::getSizeInBits(VT) == 64) return false;
   return (X86::isSplatMask(Mask.Val) ||
           (Subtarget->hasSSE2() && X86::isPSHUFDMask(Mask.Val)));
 }


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.37 llvm/lib/Target/X86/X86ISelLowering.h:1.38
--- llvm/lib/Target/X86/X86ISelLowering.h:1.37	Wed Mar 22 12:59:22 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Wed Mar 22 16:07:06 2006
@@ -267,7 +267,7 @@
     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
     /// are assumed to be legal.
-    virtual bool isShuffleMaskLegal(SDOperand Mask) const;
+    virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const;
   private:
     // C Calling Convention implementation.
     std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);