[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.173 -> 1.174
---
Log message:

With Evan's latest tblgen patch, this code is obsolete, thanks Evan!


---
Diffs of the changes:  (+0 -16)

 PPCISelDAGToDAG.cpp |   16 ----------------
 1 files changed, 16 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.174
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.173	Mon Mar 20 16:38:22 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Tue Mar 21 00:37:40 2006
@@ -944,22 +944,6 @@
   
   switch (N->getOpcode()) {
   default: break;
-  case ISD::VECTOR_SHUFFLE:
-    // FIXME: This should be autogenerated from the .td file, it is here for now
-    // due to bugs in tblgen.
-    if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
-        (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
-        PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
-      SDOperand N0;
-      Select(N0, N->getOperand(0));
-      Result = CodeGenMap[Op] = 
-        SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
-                                        getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
-                                        N0), 0);
-      return;
-    }
-    assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
-      
   case ISD::SETCC:
     Result = SelectSETCC(Op);
     return;