[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp PPCRegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCInstrInfo.cpp updated: 1.18 -> 1.19
PPCRegisterInfo.cpp updated: 1.46 -> 1.47
---
Log message:

teach the ppc backend how to spill/reload vector regs


---
Diffs of the changes:  (+21 -1)

 PPCInstrInfo.cpp    |    2 +-
 PPCRegisterInfo.cpp |   20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.19
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.18	Thu Mar 16 14:03:58 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp	Thu Mar 16 16:24:02 2006
@@ -80,7 +80,7 @@
 }
 
 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
-                                              int &FrameIndex) const {
+                                           int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
   case PPC::LD:


Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.47
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.46	Thu Mar 16 15:31:45 2006
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp	Thu Mar 16 16:24:02 2006
@@ -50,6 +50,9 @@
                                      unsigned SrcReg, int FrameIdx,
                                      const TargetRegisterClass *RC) const {
   if (SrcReg == PPC::LR) {
+    // FIXME: this spills LR immediately to memory in one step.  To do this, we
+    // use R11, which we know cannot be used in the prolog/epilog.  This is a
+    // hack.
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
     addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
   } else if (RC == PPC::CRRCRegisterClass) {
@@ -63,6 +66,15 @@
     addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
     addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
+  } else if (RC == PPC::VRRCRegisterClass) {
+    // We don't have indexed addressing for vector loads.  Emit:
+    // R11 = ADDI FI#
+    // Dest = LVX R0, R11
+    // 
+    // FIXME: We use R0 here, because it isn't available for RA.
+    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+    BuildMI(MBB, MI, PPC::STVX, 3)
+      .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();
@@ -88,6 +100,14 @@
     addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
     addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
+  } else if (RC == PPC::VRRCRegisterClass) {
+    // We don't have indexed addressing for vector loads.  Emit:
+    // R11 = ADDI FI#
+    // Dest = LVX R0, R11
+    // 
+    // FIXME: We use R0 here, because it isn't available for RA.
+    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+    BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();