[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAGList.cpp updated: 1.46 -> 1.47
---
Log message:

Chain operands aren't real uses: they don't require the full latency of the
predecessor to finish before they can start.


---
Diffs of the changes:  (+10 -4)

 ScheduleDAGList.cpp |   14 ++++++++++----
 1 files changed, 10 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.46 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.47
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.46	Sat Mar 11 18:38:57 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp	Sat Mar 11 21:52:09 2006
@@ -387,8 +387,6 @@
 }
 
 /// Schedule - Schedule the DAG using list scheduling.
-/// FIXME: Right now it only supports the burr (bottom up register reducing)
-/// heuristic.
 void ScheduleDAGList::Schedule() {
   DEBUG(std::cerr << "********** List Scheduling **********\n");
   
@@ -552,8 +550,16 @@
     unsigned AvailableCycle = 0;
     for (std::set<std::pair<SUnit*, bool> >::iterator I = SuccSU->Preds.begin(),
          E = SuccSU->Preds.end(); I != E; ++I) {
-      AvailableCycle = std::max(AvailableCycle, 
-                                I->first->Cycle + I->first->Latency);
+      // If this is a token edge, we don't need to wait for the full latency of
+      // the preceeding instruction (e.g. a long-latency load) unless there is
+      // also some other data dependence.
+      unsigned PredDoneCycle = I->first->Cycle;
+      if (!I->second)
+        PredDoneCycle += I->first->Latency;
+      else
+        PredDoneCycle += 1;  
+
+      AvailableCycle = std::max(AvailableCycle, PredDoneCycle);
     }
     
     PendingQueue.push_back(std::make_pair(AvailableCycle, SuccSU));