[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaInstrInfo.td
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Thu Mar 9 06:58:38 PST 2006
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.39 -> 1.40
AlphaInstrInfo.td updated: 1.113 -> 1.114
---
Log message:
fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses
---
Diffs of the changes: (+15 -220)
AlphaISelLowering.cpp | 165 --------------------------------------------------
AlphaInstrInfo.td | 70 ++++-----------------
2 files changed, 15 insertions(+), 220 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.39 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.40
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.39 Sat Mar 4 23:08:37 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Thu Mar 9 08:58:25 2006
@@ -26,12 +26,6 @@
using namespace llvm;
-namespace llvm {
- cl::opt<bool> EnableAlphaLSMark("enable-alpha-lsmark",
- cl::desc("Emit symbols to correlate Mem ops to LLVM Values"),
- cl::Hidden);
-}
-
/// AddLiveIn - This helper function adds the specified physical register to the
/// MachineFunction as a live in value. It also creates a corresponding virtual
/// register for it.
@@ -71,20 +65,6 @@
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
- if (EnableAlphaLSMark) {
- setOperationAction(ISD::LOAD, MVT::i64, Custom);
- setOperationAction(ISD::LOAD, MVT::f64, Custom);
- setOperationAction(ISD::LOAD, MVT::f32, Custom);
-
- setOperationAction(ISD::ZEXTLOAD, MVT::i8, Custom);
- setOperationAction(ISD::ZEXTLOAD, MVT::i16, Custom);
- setOperationAction(ISD::SEXTLOAD, MVT::i32, Custom);
-
- setOperationAction(ISD::EXTLOAD, MVT::i8, Custom);
- setOperationAction(ISD::EXTLOAD, MVT::i16, Custom);
- setOperationAction(ISD::EXTLOAD, MVT::i32, Custom);
- }
-
setOperationAction(ISD::FREM, MVT::f32, Expand);
setOperationAction(ISD::FREM, MVT::f64, Expand);
@@ -175,18 +155,6 @@
case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
case AlphaISD::CALL: return "Alpha::CALL";
case AlphaISD::DivCall: return "Alpha::DivCall";
- case AlphaISD::LDQ_: return "Alpha::LDQ_";
- case AlphaISD::LDT_: return "Alpha::LDT_";
- case AlphaISD::LDS_: return "Alpha::LDS_";
- case AlphaISD::LDL_: return "Alpha::LDL_";
- case AlphaISD::LDWU_: return "Alpha::LDWU_";
- case AlphaISD::LDBU_: return "Alpha::LDBU_";
- case AlphaISD::STQ_: return "Alpha::STQ_";
- case AlphaISD::STT_: return "Alpha::STT_";
- case AlphaISD::STS_: return "Alpha::STS_";
- case AlphaISD::STL_: return "Alpha::STL_";
- case AlphaISD::STW_: return "Alpha::STW_";
- case AlphaISD::STB_: return "Alpha::STB_";
}
}
@@ -395,48 +363,6 @@
BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
}
-
-
-static void getValueInfo(const Value* v, int& type, int& fun, int& offset)
-{
- fun = type = offset = 0;
- if (v == NULL) {
- type = 0;
- } else if (const GlobalValue* GV = dyn_cast<GlobalValue>(v)) {
- type = 1;
- const Module* M = GV->getParent();
- for(Module::const_global_iterator ii = M->global_begin(); &*ii != GV; ++ii)
- ++offset;
- } else if (const Argument* Arg = dyn_cast<Argument>(v)) {
- type = 2;
- const Function* F = Arg->getParent();
- const Module* M = F->getParent();
- for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
- ++fun;
- for(Function::const_arg_iterator ii = F->arg_begin(); &*ii != Arg; ++ii)
- ++offset;
- } else if (const Instruction* I = dyn_cast<Instruction>(v)) {
- assert(dyn_cast<PointerType>(I->getType()));
- type = 3;
- const BasicBlock* bb = I->getParent();
- const Function* F = bb->getParent();
- const Module* M = F->getParent();
- for(Module::const_iterator ii = M->begin(); &*ii != F; ++ii)
- ++fun;
- for(Function::const_iterator ii = F->begin(); &*ii != bb; ++ii)
- offset += ii->size();
- for(BasicBlock::const_iterator ii = bb->begin(); &*ii != I; ++ii)
- ++offset;
- } else if (const Constant* C = dyn_cast<Constant>(v)) {
- //Don't know how to look these up yet
- type = 0;
- } else {
- assert(0 && "Error in value marking");
- }
- //type = 4: register spilling
- //type = 5: global address loading or constant loading
-}
-
static int getUID()
{
static int id = 0;
@@ -535,97 +461,6 @@
}
break;
- case ISD::LOAD:
- case ISD::SEXTLOAD:
- case ISD::ZEXTLOAD:
- case ISD::EXTLOAD:
- {
- SDOperand Chain = Op.getOperand(0);
- SDOperand Address = Op.getOperand(1);
-
- unsigned Opc;
- unsigned opcode = Op.getOpcode();
-
- if (opcode == ISD::LOAD)
- switch (Op.Val->getValueType(0)) {
- default: Op.Val->dump(); assert(0 && "Bad load!");
- case MVT::i64: Opc = AlphaISD::LDQ_; break;
- case MVT::f64: Opc = AlphaISD::LDT_; break;
- case MVT::f32: Opc = AlphaISD::LDS_; break;
- }
- else
- switch (cast<VTSDNode>(Op.getOperand(3))->getVT()) {
- default: Op.Val->dump(); assert(0 && "Bad sign extend!");
- case MVT::i32: Opc = AlphaISD::LDL_;
- assert(opcode != ISD::ZEXTLOAD && "Not sext"); break;
- case MVT::i16: Opc = AlphaISD::LDWU_;
- assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
- case MVT::i1: //FIXME: Treat i1 as i8 since there are problems otherwise
- case MVT::i8: Opc = AlphaISD::LDBU_;
- assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
- }
-
- int i, j, k;
- getValueInfo(dyn_cast<SrcValueSDNode>(Op.getOperand(2))->getValue(), i, j, k);
-
- SDOperand Zero = DAG.getConstant(0, MVT::i64);
- std::vector<MVT::ValueType> VTS;
- VTS.push_back(Op.Val->getValueType(0));
- VTS.push_back(MVT::Other);
- std::vector<SDOperand> ARGS;
- ARGS.push_back(Chain);
- ARGS.push_back(Zero);
- ARGS.push_back(Address);
- ARGS.push_back(DAG.getConstant(i, MVT::i64));
- ARGS.push_back(DAG.getConstant(j, MVT::i64));
- ARGS.push_back(DAG.getConstant(k, MVT::i64));
- ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
- return DAG.getNode(Opc, VTS, ARGS);
- }
-
- case ISD::TRUNCSTORE:
- case ISD::STORE:
- {
- SDOperand Chain = Op.getOperand(0);
- SDOperand Value = Op.getOperand(1);
- SDOperand Address = Op.getOperand(2);
-
- unsigned Opc;
- unsigned opcode = Op.getOpcode();
-
- if (opcode == ISD::STORE) {
- switch(Value.getValueType()) {
- default: assert(0 && "unknown Type in store");
- case MVT::i64: Opc = AlphaISD::STQ_; break;
- case MVT::f64: Opc = AlphaISD::STT_; break;
- case MVT::f32: Opc = AlphaISD::STS_; break;
- }
- } else { //ISD::TRUNCSTORE
- switch(cast<VTSDNode>(Op.getOperand(4))->getVT()) {
- default: assert(0 && "unknown Type in store");
- case MVT::i8: Opc = AlphaISD::STB_; break;
- case MVT::i16: Opc = AlphaISD::STW_; break;
- case MVT::i32: Opc = AlphaISD::STL_; break;
- }
- }
-
- int i, j, k;
- getValueInfo(cast<SrcValueSDNode>(Op.getOperand(3))->getValue(), i, j, k);
-
- SDOperand Zero = DAG.getConstant(0, MVT::i64);
- std::vector<MVT::ValueType> VTS;
- VTS.push_back(MVT::Other);
- std::vector<SDOperand> ARGS;
- ARGS.push_back(Chain);
- ARGS.push_back(Value);
- ARGS.push_back(Zero);
- ARGS.push_back(Address);
- ARGS.push_back(DAG.getConstant(i, MVT::i64));
- ARGS.push_back(DAG.getConstant(j, MVT::i64));
- ARGS.push_back(DAG.getConstant(k, MVT::i64));
- ARGS.push_back(DAG.getConstant(getUID(), MVT::i64));
- return DAG.getNode(Opc, VTS, ARGS);
- }
case ISD::VAARG: {
SDOperand Chain = Op.getOperand(0);
SDOperand VAListP = Op.getOperand(1);
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.113 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.114
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.113 Thu Feb 2 21:07:37 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Thu Mar 9 08:58:25 2006
@@ -19,13 +19,6 @@
def SDTFPUnaryOpUnC : SDTypeProfile<1, 1, [
SDTCisFP<1>, SDTCisFP<0>
]>;
-def SDTLoadA : SDTypeProfile<1, 6, [ // load
- SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
-]>;
-def SDTStoreA : SDTypeProfile<0, 7, [ // load
- SDTCisInt<1>, SDTCisPtrTy<2>, SDTCisInt<3>, SDTCisInt<4>, SDTCisInt<5>, SDTCisInt<6>
-]>;
-
def Alpha_itoft : SDNode<"AlphaISD::ITOFT_", SDTIntToFPOp, []>;
def Alpha_ftoit : SDNode<"AlphaISD::FTOIT_", SDTFPToIntOp, []>;
def Alpha_cvtqt : SDNode<"AlphaISD::CVTQT_", SDTFPUnaryOpUnC, []>;
@@ -34,18 +27,6 @@
def Alpha_gprello : SDNode<"AlphaISD::GPRelLo", SDTIntBinOp, []>;
def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi", SDTIntBinOp, []>;
def Alpha_rellit : SDNode<"AlphaISD::RelLit", SDTIntBinOp, []>;
-def Alpha_ldq : SDNode<"AlphaISD::LDQ_", SDTLoadA, [SDNPHasChain]>;
-def Alpha_ldt : SDNode<"AlphaISD::LDT_", SDTLoadA, [SDNPHasChain]>;
-def Alpha_lds : SDNode<"AlphaISD::LDS_", SDTLoadA, [SDNPHasChain]>;
-def Alpha_ldl : SDNode<"AlphaISD::LDL_", SDTLoadA, [SDNPHasChain]>;
-def Alpha_ldwu : SDNode<"AlphaISD::LDWU_", SDTLoadA, [SDNPHasChain]>;
-def Alpha_ldbu : SDNode<"AlphaISD::LDBU_", SDTLoadA, [SDNPHasChain]>;
-def Alpha_stq : SDNode<"AlphaISD::STQ_", SDTStoreA, [SDNPHasChain]>;
-def Alpha_stl : SDNode<"AlphaISD::STL_", SDTStoreA, [SDNPHasChain]>;
-def Alpha_stw : SDNode<"AlphaISD::STW_", SDTStoreA, [SDNPHasChain]>;
-def Alpha_stb : SDNode<"AlphaISD::STB_", SDTStoreA, [SDNPHasChain]>;
-def Alpha_sts : SDNode<"AlphaISD::STS_", SDTStoreA, [SDNPHasChain]>;
-def Alpha_stt : SDNode<"AlphaISD::STT_", SDTStoreA, [SDNPHasChain]>;
// These are target-independent nodes, but have target-specific formats.
def SDT_AlphaCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i64> ]>;
@@ -569,38 +550,6 @@
(LDQl texternalsym:$ext, GPRC:$RB)>;
-//Various tracked versions
-let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB,
- s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in {
-def LDQlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldq $RA,$DISP($RB)",
- [(set GPRC:$RA, (Alpha_ldq imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-def LDLlbl : MForm<0x28, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldl $RA,$DISP($RB)",
- [(set GPRC:$RA, (Alpha_ldl imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-def LDBUlbl : MForm<0x0A, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldbu $RA,$DISP($RB)",
- [(set GPRC:$RA, (Alpha_ldwu imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-def LDWUlbl : MForm<0x0C, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldwu $RA,$DISP($RB)",
- [(set GPRC:$RA, (Alpha_ldbu imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-
-def STBlbl : MForm<0x0E, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stb $RA,$DISP($RB)",
- [(Alpha_stb GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
-def STWlbl : MForm<0x0D, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stw $RA,$DISP($RB)",
- [(Alpha_stw GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
-def STLlbl : MForm<0x2C, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stl $RA,$DISP($RB)",
- [(Alpha_stl GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
-def STQlbl : MForm<0x2D, 1, 0, "LSMARKER$$$i$$$j$$$k$$$m:\n\t stq $RA,$DISP($RB)",
- [(Alpha_stq GPRC:$RA, imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m)]>;
-}
-
-let OperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB,
- s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
-def LDTlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t ldt $RA,$DISP($RB)",
- [(set F8RC:$RA, (Alpha_ldt imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-
-let OperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB,
- s64imm:$i, s64imm:$j, s64imm:$k, s64imm:$m) in
-def LDSlbl : MForm<0x29, 0, 1, "LSMARKER$$$i$$$j$$$k$$$m:\n\t lds $RA,$DISP($RB)",
- [(set F4RC:$RA, (Alpha_lds imm:$DISP, GPRC:$RB, imm:$i, imm:$j, imm:$k, imm:$m))]>;
-
def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter
//Basic Floating point ops
@@ -621,9 +570,12 @@
def MULS : FPForm<0x16, 0x582, "muls/su $RA,$RB,$RC",
[(set F4RC:$RC, (fmul F4RC:$RA, F4RC:$RB))]>;
-def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
+def CPYSS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
+ [(set F4RC:$RC, (fcopysign F4RC:$RA, F4RC:$RB))]>;
def CPYSES : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
-def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
+//FIXME: This might be legalized in the oposite manner
+def CPYSNS : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
+ [(set F4RC:$RC, (fneg (fcopysign F4RC:$RA, F4RC:$RB)))]>;
}
//Doubles
@@ -642,9 +594,12 @@
def MULT : FPForm<0x16, 0x5A2, "mult/su $RA,$RB,$RC",
[(set F8RC:$RC, (fmul F8RC:$RA, F8RC:$RB))]>;
-def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",[]>; //Copy sign
+def CPYST : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC",
+ [(set F8RC:$RC, (fcopysign F8RC:$RA, F8RC:$RB))]>;
def CPYSET : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC",[]>; //Copy sign and exponent
-def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",[]>; //Copy sign negate
+//FIXME: This might be legalized in the oposite manner
+def CPYSNT : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC",
+ [(set F8RC:$RC, (fneg (fcopysign F8RC:$RA, F8RC:$RB)))]>;
def CMPTEQ : FPForm<0x16, 0x5A5, "cmpteq/su $RA,$RB,$RC", []>;
// [(set F8RC:$RC, (seteq F8RC:$RA, F8RC:$RB))]>;
@@ -895,6 +850,11 @@
(CPYSNT F8RC:$RB, F8RC:$RB)>;
def : Pat<(fneg F4RC:$RB),
(CPYSNS F4RC:$RB, F4RC:$RB)>;
+def : Pat<(fcopysign (fneg F4RC:$A), F4RC:$B),
+ (CPYSNS F4RC:$A, F4RC:$B)>;
+def : Pat<(fcopysign (fneg F8RC:$A), F8RC:$B),
+ (CPYSNT F8RC:$A, F8RC:$B)>;
+
//Yes, signed multiply high is ugly
def : Pat<(mulhs GPRC:$RA, GPRC:$RB),
(SUBQ (UMULH GPRC:$RA, GPRC:$RB), (ADDQ (CMOVGE GPRC:$RB, R31, GPRC:$RA),
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