[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGList.cpp SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.72 -> 1.73
ScheduleDAGList.cpp updated: 1.20 -> 1.21
SelectionDAGISel.cpp updated: 1.181 -> 1.182
---
Log message:

Change the interface for getting a target HazardRecognizer to be more clean.


---
Diffs of the changes:  (+15 -18)

 ScheduleDAG.cpp      |    2 +-
 ScheduleDAGList.cpp  |   23 +++++++++++------------
 SelectionDAGISel.cpp |    8 +++-----
 3 files changed, 15 insertions(+), 18 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.72 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.73
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.72	Sun Mar  5 17:51:47 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Tue Mar  7 22:25:44 2006
@@ -14,9 +14,9 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "sched"
+#include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.20 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.21
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.20	Mon Mar  6 23:40:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp	Tue Mar  7 22:25:44 2006
@@ -178,7 +178,7 @@
   bool isBottomUp;
   
   /// HazardRec - The hazard recognizer to use.
-  HazardRecognizer &HazardRec;
+  HazardRecognizer *HazardRec;
   
   typedef std::priority_queue<SUnit*, std::vector<SUnit*>, ls_rr_sort>
     AvailableQueueTy;
@@ -186,7 +186,7 @@
 public:
   ScheduleDAGList(SelectionDAG &dag, MachineBasicBlock *bb,
                   const TargetMachine &tm, bool isbottomup,
-                  HazardRecognizer &HR)
+                  HazardRecognizer *HR)
     : ScheduleDAG(listSchedulingBURR, dag, bb, tm),
       CurrCycle(0), HeadSUnit(NULL), TailSUnit(NULL), isBottomUp(isbottomup),
       HazardRec(HR) {
@@ -199,6 +199,7 @@
       delete SU;
       SU = NextSU;
     }
+    delete HazardRec;
   }
 
   void Schedule();
@@ -413,12 +414,10 @@
   // Available queue.
   AvailableQueueTy Available;
 
-  HazardRec.StartBasicBlock();
-  
   // Emit the entry node first.
   SUnit *Entry = SUnitMap[DAG.getEntryNode().Val];
   ScheduleNodeTopDown(Available, Entry);
-  HazardRec.EmitInstruction(Entry->Node);
+  HazardRec->EmitInstruction(Entry->Node);
                       
   // All leaves to Available queue.
   for (SUnit *SU = HeadSUnit; SU != NULL; SU = SU->Next) {
@@ -446,7 +445,7 @@
            N->getOpcode() < ISD::BUILTIN_OP_END && i != e; ++i)
         N = CurNode->FlaggedNodes[i];
       
-      HazardRecognizer::HazardType HT = HazardRec.getHazardType(N);
+      HazardRecognizer::HazardType HT = HazardRec->getHazardType(N);
       if (HT == HazardRecognizer::NoHazard) {
         FoundNode = CurNode;
         break;
@@ -467,19 +466,19 @@
     // If we found a node to schedule, do it now.
     if (FoundNode) {
       ScheduleNodeTopDown(Available, FoundNode);
-      HazardRec.EmitInstruction(FoundNode->Node);
+      HazardRec->EmitInstruction(FoundNode->Node);
     } else if (!HasNoopHazards) {
       // Otherwise, we have a pipeline stall, but no other problem, just advance
       // the current cycle and try again.
       DEBUG(std::cerr << "*** Advancing cycle, no work to do\n");
-      HazardRec.AdvanceCycle();
+      HazardRec->AdvanceCycle();
       ++NumStalls;
     } else {
       // Otherwise, we have no instructions to issue and we have instructions
       // that will fault if we don't do this right.  This is the case for
       // processors without pipeline interlocks and other cases.
       DEBUG(std::cerr << "*** Emitting noop\n");
-      HazardRec.EmitNoop();
+      HazardRec->EmitNoop();
       Sequence.push_back(0);   // NULL SUnit* -> noop
       ++NumNoops;
     }
@@ -691,14 +690,14 @@
 
 llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAG &DAG,
                                                     MachineBasicBlock *BB) {
-  HazardRecognizer HR;
-  return new ScheduleDAGList(DAG, BB, DAG.getTarget(), true, HR);
+  return new ScheduleDAGList(DAG, BB, DAG.getTarget(), true, 
+                             new HazardRecognizer());
 }
 
 /// createTDListDAGScheduler - This creates a top-down list scheduler with the
 /// specified hazard recognizer.
 ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAG &DAG,
                                             MachineBasicBlock *BB,
-                                            HazardRecognizer &HR) {
+                                            HazardRecognizer *HR) {
   return new ScheduleDAGList(DAG, BB, DAG.getTarget(), false, HR);
 }


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.181 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.182
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.181	Sun Mar  5 18:22:00 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Mar  7 22:25:44 2006
@@ -2474,17 +2474,15 @@
     SL = createBURRListDAGScheduler(DAG, BB);
     break;
   case listSchedulingTD:
-    SL = createTDListDAGScheduler(DAG, BB, GetTargetHazardRecognizer());
+    SL = createTDListDAGScheduler(DAG, BB, CreateTargetHazardRecognizer());
     break;
   }
   BB = SL->Run();
   delete SL;
 }
 
-HazardRecognizer &SelectionDAGISel::
-GetTargetHazardRecognizer() {
-  static HazardRecognizer DefaultRecognizer;
-  return DefaultRecognizer;
+HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
+  return new HazardRecognizer();
 }
 
 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated