[llvm-commits] CVS: llvm/lib/Target/PowerPC/README.txt

Chris Lattner lattner at cs.uiuc.edu
Mon Mar 6 20:43:11 PST 2006

Changes in directory llvm/lib/Target/PowerPC:

README.txt updated: 1.68 -> 1.69
Log message:

add a note

Diffs of the changes:  (+14 -0)

 README.txt |   14 ++++++++++++++
 1 files changed, 14 insertions(+)

Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.68 llvm/lib/Target/PowerPC/README.txt:1.69
--- llvm/lib/Target/PowerPC/README.txt:1.68	Wed Mar  1 00:36:20 2006
+++ llvm/lib/Target/PowerPC/README.txt	Mon Mar  6 22:42:59 2006
@@ -452,3 +452,17 @@
         srwi r3, r2, 24
+On the G5, logical CR operations are more expensive in their three
+address form: ops that read/write the same register are half as expensive as
+those that read from two registers that are different from their destination.
+We should model this with two separate instructions.  The isel should generate
+the "two address" form of the instructions.  When the register allocator 
+detects that it needs to insert a copy due to the two-addresness of the CR
+logical op, it will invoke PPCInstrInfo::convertToThreeAddress.  At this point
+we can convert to the "three address" instruction, to save code space.
+This only matters when we start generating cr logical ops.

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